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A frequency steered phase locked loop

1997 IEEE International Performance, Computing and Communications Conference, 1997
Voltage controlled oscillators (VCOs) implemented in digital VLSI IC (integrated circuit) technology typically have very poorly controlled centre frequencies and poor phase noise characteristics, thus severely limiting their use in phase locked loop (PLL) applications.
Martin T. Hill, Antonio Cantoni
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Digital phase-locked loops

2018 IEEE Custom Integrated Circuits Conference (CICC), 2018
▪ Digital PLLs exploit CMOS scaling and allow accurate cancellation of fractional spurs and automatic bandwidth control ▪ In Bang-Bang DPLLs assisted by DTC, performance is only limited by DCO and DTC resolution ▪ Bang-Bang DPLLs assisted by DTC allow same phase-noise performance and fractionalspur level as standard DPLLs at much lower power ...
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Hangup in Phase-Lock Loops

IEEE Transactions on Communications, 1977
A phase-lock loop occasionally will take a long time to settle to equilibrium. Phase dwells at a large error for a prolonged interval. This phenomenon has been dubbed "hangup." The periodic nature of phase detectors is responsible for hangup, which occurs near the reverse-slope, unstable null.
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A digital loop filter for a Phase Locked Loop

2011 17th International Conference on Digital Signal Processing (DSP), 2011
Modern digital telecommunication and audio systems include a Digital Phase Locked Loop (D-PLL) in a form of a device or an algorithm. Wireless infrastructure, broadband wire-line networks and high end audio systems require very high performance PLLs.
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On the Pull-In Range of Phase-Locked Loops

IEEE Transactions on Communications, 1975
The problem of determining the pull-in range of phaselocked loops is solved indirectly by evaluating the limit cycles of the loop in which the frequency error has a constant average. The analytical results derived here are in complete agreement with simulation results.
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On Stochastic Phase-Lock Loop Solutions

IEEE Transactions on Communications, 1976
The solutions to stochastic first- and second-order phaselock loop differential equations are studied in the sense of the calculus of Ito and Stratonovich. The solutions are found to be both theoretically and experimentally invariant to the calculus used.
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Phase-Locked Loops

2002
In this chapter we describe an important electronic circuit, the phase-locked loop (PLL). We first investigate the circuit’s dynamics without and with random perturbations, but in the absence of external forcing. Then we analyze the response of the circuit to noisy external signals, and we describe a method for extracting signals from the result.
Anatoli V. Skorokhod   +2 more
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Phase-Locked Loops

1991
A phase-locked loop (PLL) is an electronic system which synchronizes an internal oscillator, in frequency and phase, with an external signal. As brought out below, the PLL is extremely useful for signal processing and signal synthesis [41]. PLLs have been used extensively in the electronic tuning of radios and in the signal processing within TVs. Today,
Donald O. Pederson, Kartikeya Mayaram
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Phase Locked Loops

Proceedings of the IEEE, 1975
A phase locked loop, (PLL), is basically a closed loop feedback system, the action of which is to lock or synchronise the frequency of a controlled oscillator to that of an incoming signal. Phase lock principles are by no means new, synchronous reception of radio signals using PLL techniques was described as early as 1932.
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A Digital BIST for Phase-Locked Loops

2008 IEEE International Symposium on Defect and Fault Tolerance of VLSI Systems, 2008
This paper presents a conceptual implementation of a jitter measurement circuit with several BIST (built-in self test) features for embedded phase-locked loops. We demonstrate a fully functional jitter measurement circuit capable of detecting cycle-to-cycle jitter.
Kevin Sliech, Martin Margala
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