Phase-locked loops - Open Access .click

2008 15th IEEE International Conference on Electronics, Circuits and Systems, 2008
The symbol synchronizer recoveries the clock and after, with it, samples and retimes the data. We present two synchronizer groups, the first based on filter with carrier phase lock loop (CPLL) and the second based on symbol phase lock loop (SPLL). Each group has four prototypes namely the analog, the hybrid, the combinational and the sequential.
Antonio D. Reis +3 more
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A Molecular Phase-Locked Loop

Proceedings of ACM The First Annual International Conference on Nanoscale Computing and Communication, 2014
Molecular communications has been considered as a new paradigm in nano-networks. Similar to classical wireless communications, molecular communications also consists of three modules, i.e., the transmitter, the signal propagation (channel) and the receiver.
Chieh Lo, Yao-Jen Liang, Kwang-Cheng Chen +2 more
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Digital phase locked loop

ICASSP '78. IEEE International Conference on Acoustics, Speech, and Signal Processing, 2005
This paper deals with the design, construction and evaluation of a Digital Phase-Locked Loop. An exclusive OR gate serves as a linear phase detector. The integrator consists of a cascade of up/down decade counters. The D.C. value of each cycle from the phase detector is measured and accumulated. The rate of integration is determined by the clock input.
C. P. Reddy, Erik Fountain
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phase locked loops
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phase-locked loop
synchronization

frequency locked loops
cmos
phase-locked loop pll