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A State-Space Framework for Parallelizing Digital Signal Processing in Coherent Optical Receivers. [PDF]
Sensors (Basel)Wang J, Wang Z, Liu D.
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I Can't Hear You Both at the Same Time: A Temporal Dilemma During Inter-Regional Communication. [PDF]
eNeuroBhat S, Ten Oever S.
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An Observer-Data-Path Decoupled Time-Domain ADC with Three-Stage Digital Background Calibration in 28 nm CMOS. [PDF]
Micromachines (Basel)Qin C, Liu B, Wang R, Li L, Zhang C.
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Seamless grid following and grid forming inverter mode transition enabled by machine-learning based SCR estimation and smooth switching control. [PDF]
Sci RepRajamallaiah A +6 more
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Synchronizers based on carrier phase lock Loop and on symbol phase lock loop
2008 15th IEEE International Conference on Electronics, Circuits and Systems, 2008The symbol synchronizer recoveries the clock and after, with it, samples and retimes the data. We present two synchronizer groups, the first based on filter with carrier phase lock loop (CPLL) and the second based on symbol phase lock loop (SPLL). Each group has four prototypes namely the analog, the hybrid, the combinational and the sequential.
Antonio D. Reis +3 more
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Proceedings of ACM The First Annual International Conference on Nanoscale Computing and Communication, 2014
Molecular communications has been considered as a new paradigm in nano-networks. Similar to classical wireless communications, molecular communications also consists of three modules, i.e., the transmitter, the signal propagation (channel) and the receiver.
Chieh Lo +2 more
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Molecular communications has been considered as a new paradigm in nano-networks. Similar to classical wireless communications, molecular communications also consists of three modules, i.e., the transmitter, the signal propagation (channel) and the receiver.
Chieh Lo +2 more
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ICASSP '78. IEEE International Conference on Acoustics, Speech, and Signal Processing, 2005
This paper deals with the design, construction and evaluation of a Digital Phase-Locked Loop. An exclusive OR gate serves as a linear phase detector. The integrator consists of a cascade of up/down decade counters. The D.C. value of each cycle from the phase detector is measured and accumulated. The rate of integration is determined by the clock input.
C. P. Reddy, Erik Fountain
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This paper deals with the design, construction and evaluation of a Digital Phase-Locked Loop. An exclusive OR gate serves as a linear phase detector. The integrator consists of a cascade of up/down decade counters. The D.C. value of each cycle from the phase detector is measured and accumulated. The rate of integration is determined by the clock input.
C. P. Reddy, Erik Fountain
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2018 IEEE Custom Integrated Circuits Conference (CICC), 2018
▪ Digital PLLs exploit CMOS scaling and allow accurate cancellation of fractional spurs and automatic bandwidth control ▪ In Bang-Bang DPLLs assisted by DTC, performance is only limited by DCO and DTC resolution ▪ Bang-Bang DPLLs assisted by DTC allow same phase-noise performance and fractionalspur level as standard DPLLs at much lower power ...
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▪ Digital PLLs exploit CMOS scaling and allow accurate cancellation of fractional spurs and automatic bandwidth control ▪ In Bang-Bang DPLLs assisted by DTC, performance is only limited by DCO and DTC resolution ▪ Bang-Bang DPLLs assisted by DTC allow same phase-noise performance and fractionalspur level as standard DPLLs at much lower power ...
openaire +1 more source