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Synchronizers based on carrier phase lock Loop and on symbol phase lock loop
2008 15th IEEE International Conference on Electronics, Circuits and Systems, 2008The symbol synchronizer recoveries the clock and after, with it, samples and retimes the data. We present two synchronizer groups, the first based on filter with carrier phase lock loop (CPLL) and the second based on symbol phase lock loop (SPLL). Each group has four prototypes namely the analog, the hybrid, the combinational and the sequential.
Antonio D. Reis +3 more
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ICASSP '78. IEEE International Conference on Acoustics, Speech, and Signal Processing, 2005
This paper deals with the design, construction and evaluation of a Digital Phase-Locked Loop. An exclusive OR gate serves as a linear phase detector. The integrator consists of a cascade of up/down decade counters. The D.C. value of each cycle from the phase detector is measured and accumulated. The rate of integration is determined by the clock input.
C. P. Reddy, Erik Fountain
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This paper deals with the design, construction and evaluation of a Digital Phase-Locked Loop. An exclusive OR gate serves as a linear phase detector. The integrator consists of a cascade of up/down decade counters. The D.C. value of each cycle from the phase detector is measured and accumulated. The rate of integration is determined by the clock input.
C. P. Reddy, Erik Fountain
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Proceedings of ACM The First Annual International Conference on Nanoscale Computing and Communication, 2014
Molecular communications has been considered as a new paradigm in nano-networks. Similar to classical wireless communications, molecular communications also consists of three modules, i.e., the transmitter, the signal propagation (channel) and the receiver.
Chieh Lo +2 more
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Molecular communications has been considered as a new paradigm in nano-networks. Similar to classical wireless communications, molecular communications also consists of three modules, i.e., the transmitter, the signal propagation (channel) and the receiver.
Chieh Lo +2 more
openaire +1 more source
A comparison of Phase Locked Loop and FIFO Locked Loop
2013 IEEE 56th International Midwest Symposium on Circuits and Systems (MWSCAS), 2013In this paper we present a comparison of two methods to control the reading frequency of a First In First Out (FIFO) memory. The first method is based on the monitoring of its filling level and the other uses the synthesis of the writing frequency to generate and control the reading frequency.
Fábio Renato Bassan +4 more
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2024 Asia Pacific Conference on Innovation in Technology (APCIT)
Abstract of US2006164137 A phase locked loop comprising a phase detector ( 100 ) for determining a phase difference between a reference signal (Ref) and mutually phase shifted signals (I, Q) to generate frequency control signals (U, D), the phase detector ( 100 ) comprising: means ( 10 ) for obtaining a first one of said frequency control signals (U, D)
van de Beek, R.C.H. +3 more
+4 more sources
Abstract of US2006164137 A phase locked loop comprising a phase detector ( 100 ) for determining a phase difference between a reference signal (Ref) and mutually phase shifted signals (I, Q) to generate frequency control signals (U, D), the phase detector ( 100 ) comprising: means ( 10 ) for obtaining a first one of said frequency control signals (U, D)
van de Beek, R.C.H. +3 more
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A Fast-Locking Digital Phase-Locked Loop
Third International Conference on Information Technology: New Generations (ITNG'06), 2006A conventional digital phase-locked loop (DPLL) is designed using (Baker et al., 2003) to operate at 1GHz using 0.18 mum CMOS technology; its lock time is 4.19 mus. By adding a coarse/fine tuning control unit composed of a digital-to-analog converter (DAC) and a counter as well as switching the currents of the charge pump, a fast-locking DPLL results ...
Mahmoud Fawzy Wagdy, Srishti Vaishnava
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