Results 131 to 140 of about 2,126 (187)

Efficient digital techniques for implementing a class of fast phase-locked loops (PLL's)

IEEE Transactions on Industrial Electronics, 1996
Circuit configurations making use of counters are described to efficiently implement controllers for time-optimal and finite-time responses in phase-locked loops (PLLs). The new PLLs, solving the responsiveness problem with conventional PLLs, require quite complicated operations, including adders and subtracters.
Fuminori Kobayashi, Masayuki Haratsu, Masateru Yabumoto, Michio Nakano   +3 more
openaire   +1 more source

ASIC clock distribution using a phase locked loop (PLL)

[1991] Proceedings Fourth Annual IEEE International ASIC Conference and Exhibit, 2002
Transferring data between ASIC chips at frequencies above 40 MHz requires special on-chip circuitry in current sub-micron technologies. Phase locked loops can provide clock skew management in ASIC devices to help compensate for clock tree insertion delays and process, temperature and voltage variations allowing maximum multi-chip system performance. >
openaire   +1 more source

Computer simulation and parameter optimization of phase-locked loops (PLL)

SIMULATION, 1971
The automatic control and simulation of phased- locked loops (PLL) is treated with particular em phasis on the use of analog and digital computer simulation techniques. The object is to obtain an adequate mathematical model for the PLL and then to use this model to optimize parameters and investi gate pull-in performance.
openaire   +1 more source

Stabilizing Condition of Grid-Connected VSC as Affected by Phase Locked Loop (PLL)

IEEE Transactions on Power Delivery, 2022
Zhengchun Du, Yujun Li
exaly  

Synchronous reference frame single‐phase phase‐locked loop (PLL) algorithm based on half‐cycle DFT

IET Power Electronics, 2020
Yezhao Liu, Tao Xia, Xu Zhang
exaly  

Phase lock loops (PLLS) and methods of initializing PLLS

2021
MAR WING, ZINGG RETO
openaire   +1 more source

Optimization analysis on the bandwidth algorithm for the phase-locked loop (PLL) in OTU

Optik, 2012
Jianguo Yuan
exaly  

Reduction of Phase Noise and Lock Time in Low Power Phase Lock Loop (PLL)

Journal of Computational and Theoretical Nanoscience, 2018
Amit Kumar, Shailendra Singh Ojha, Shyam Akashe   +2 more
openaire   +1 more source

A study of third-order Phase-Locked Loop (PLL) systems

2008
Master of Science (Consumer Electronics)
openaire   +1 more source

The Phase-locked Loop (PLL)

2019
openaire   +1 more source