Results 201 to 210 of about 7,499 (263)
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ICASSP '78. IEEE International Conference on Acoustics, Speech, and Signal Processing, 2005
This paper deals with the design, construction and evaluation of a Digital Phase-Locked Loop. An exclusive OR gate serves as a linear phase detector. The integrator consists of a cascade of up/down decade counters. The D.C. value of each cycle from the phase detector is measured and accumulated. The rate of integration is determined by the clock input.
C. P. Reddy, Erik Fountain
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This paper deals with the design, construction and evaluation of a Digital Phase-Locked Loop. An exclusive OR gate serves as a linear phase detector. The integrator consists of a cascade of up/down decade counters. The D.C. value of each cycle from the phase detector is measured and accumulated. The rate of integration is determined by the clock input.
C. P. Reddy, Erik Fountain
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Lock Detection in Phase-Locked Loops
SIAM Journal on Applied Mathematics, 1992The phase quadrature lock detector is used extensively to detect phase lock in phase-locked loops (PLLs). However, this lock detector's relationship to PLL closed-loop dynamics has never been established. A new theory is presented, which accomplishes this for a specified class of PLLs.
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A Fast-Locking Digital Phase-Locked Loop
Third International Conference on Information Technology: New Generations (ITNG'06), 2006A conventional digital phase-locked loop (DPLL) is designed using (Baker et al., 2003) to operate at 1GHz using 0.18 mum CMOS technology; its lock time is 4.19 mus. By adding a coarse/fine tuning control unit composed of a digital-to-analog converter (DAC) and a counter as well as switching the currents of the charge pump, a fast-locking DPLL results ...
Mahmoud Fawzy Wagdy, Srishti Vaishnava
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2018 IEEE Custom Integrated Circuits Conference (CICC), 2018
▪ Digital PLLs exploit CMOS scaling and allow accurate cancellation of fractional spurs and automatic bandwidth control ▪ In Bang-Bang DPLLs assisted by DTC, performance is only limited by DCO and DTC resolution ▪ Bang-Bang DPLLs assisted by DTC allow same phase-noise performance and fractionalspur level as standard DPLLs at much lower power ...
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▪ Digital PLLs exploit CMOS scaling and allow accurate cancellation of fractional spurs and automatic bandwidth control ▪ In Bang-Bang DPLLs assisted by DTC, performance is only limited by DCO and DTC resolution ▪ Bang-Bang DPLLs assisted by DTC allow same phase-noise performance and fractionalspur level as standard DPLLs at much lower power ...
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Fast lock scheme for phase-locked loops
2009 IEEE Custom Integrated Circuits Conference, 2009This paper describes a fast lock scheme for phaselocked loops (PLLs). The proposed scheme utilizes mostly digital logic and control to achieve significant reduction in PLL lock acquisition time, which enables dynamic power cycling for various sub-systems on SOC designs.
Amir Bashir +6 more
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IEEE Transactions on Communications, 1977
A phase-lock loop occasionally will take a long time to settle to equilibrium. Phase dwells at a large error for a prolonged interval. This phenomenon has been dubbed "hangup." The periodic nature of phase detectors is responsible for hangup, which occurs near the reverse-slope, unstable null.
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A phase-lock loop occasionally will take a long time to settle to equilibrium. Phase dwells at a large error for a prolonged interval. This phenomenon has been dubbed "hangup." The periodic nature of phase detectors is responsible for hangup, which occurs near the reverse-slope, unstable null.
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A frequency steered phase locked loop
1997 IEEE International Performance, Computing and Communications Conference, 1997Voltage controlled oscillators (VCOs) implemented in digital VLSI IC (integrated circuit) technology typically have very poorly controlled centre frequencies and poor phase noise characteristics, thus severely limiting their use in phase locked loop (PLL) applications.
Martin T. Hill, Antonio Cantoni
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IECON 2012 - 38th Annual Conference on IEEE Industrial Electronics Society, 2012
This paper proposes a new three-phase software phase-locked loop (SPLL) which operates fast and accurately in unbalanced, polluted and frequency deviated circumstances. This new proposed SPLL consists of frequency-locked loop (FLL) and initial phase angle detection PLL. The FLL employs differential algorithm to detect frequency error which could immune
Liang Wang, Qirong Jiang, Lucheng Hong
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This paper proposes a new three-phase software phase-locked loop (SPLL) which operates fast and accurately in unbalanced, polluted and frequency deviated circumstances. This new proposed SPLL consists of frequency-locked loop (FLL) and initial phase angle detection PLL. The FLL employs differential algorithm to detect frequency error which could immune
Liang Wang, Qirong Jiang, Lucheng Hong
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False Lock and Bifurcation in the Phase Locked Loop
SIAM Journal on Applied Mathematics, 1987New results are given on the phenomenon of false lock in phase locked loops (PLL). First, it is proved that for small values of closed loop gain \(\delta\), there is only one function \(\omega_ f(\delta)\) which represents the frequency error in a false locked Type 1 PLL.
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A digital loop filter for a Phase Locked Loop
2011 17th International Conference on Digital Signal Processing (DSP), 2011Modern digital telecommunication and audio systems include a Digital Phase Locked Loop (D-PLL) in a form of a device or an algorithm. Wireless infrastructure, broadband wire-line networks and high end audio systems require very high performance PLLs.
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