Results 31 to 40 of about 65,747 (300)
Mathematical models and simulations of phase noise in phase-locked loops [PDF]
Songklanakarin Journal of Science and Technology (SJST), 2007 Phase noises in Phase-Locked Loops (PLLs) are a key parameter for communication systems that contribute the bit-rate-error of communication systems and cause synchronization problems.
Sethapong Limkumnerd +1 more
doaj
All‐digital built‐in self‐test scheme for charge‐pump phase‐locked loops
IET Circuits, Devices and Systems, 2021 Charge‐pump phase‐locked loop (CP‐PLL) is widely used to generate timing signals in systems on chips (SoCs). However, the number of cores embedded in SoCs, the limited I/O port resources and the cost of external test equipment lead to the increase of ...
Lanhua Xia, Jifei Tang
doaj +1 more source
Oscillation quenching in third order Phase Locked Loop coupled by mean field diffusive coupling
, 2016 We explore analytically the oscillation quenching phenomena (amplitude death and oscillation death) in a coupled third order phase locked loop (PLL) both in periodic and chaotic mode.
Chakraborty, S +2 more
core +1 more source
Lessons Learned From a Delayed‐Start Trial of Modafinil for Freezing of Gait in Parkinson's Disease
Annals of Clinical and Translational Neurology, EarlyView.ABSTRACT Objective Freezing of gait (FOG) in people with Parkinson's disease (PwPD) is debilitating and has limited treatments. Modafinil modulates beta/gamma band activity in the pedunculopontine nucleus (PPN), like PPN deep brain stimulation. We therefore tested the hypothesis that Modafinil would improve FOG in PwPD.
Tuhin Virmani +8 more
wiley +1 more source
IEEE Access, 2021 Synchronization is the key part to ensure the high performance of grid-connected systems. Phase-locked loop (PLL) is one of the most popular synchronizations due to its simple implementation and robustness under certain grid variations.
Jinming Xu +4 more
doaj +1 more source
Ultrasound array transmitter architecture with high timing resolution using embedded phase-locked loops [PDF]
, 2012 Coarse time quantization of delay profiles within ultrasound array systems can produce undesirable sidelobes in the radiated beam profile. The severity of these sidelobes is dependent upon the magnitude of phase quantization error - the deviation from ...
Cowell, DMJ +4 more
core +1 more source
Annals of Clinical and Translational Neurology, EarlyView.ABSTRACT Objective Status epilepticus (SE) is associated with significant mortality. Sleep architecture may reflect normal brain function. Impaired sleep architecture is associated with poorer outcomes in numerous conditions. Here we investigate the association of sleep architecture in continuous EEG (cEEG) with survival in SE.
Ran R. Liu +5 more
wiley +1 more source
Synchronization in networks of mutually delay-coupled phase-locked loops
New Journal of Physics, 2014 Electronic components that perform tasks in a concerted way rely on a common time reference. For instance, parallel computing demands synchronous clocking of multiple cores or processors to reliably carry out joint computations.
Alexandros Pollakis +5 more
doaj +1 more source
Phase demodulation system with two phase locked loops Patent [PDF]
, 1970 Development of phase demodulation system with two phase locked ...
Hudspeth, T.
core +1 more source
Dynamic phasor analysis and design of phase-locked loops for single phase grid connected converters [PDF]
, 2015 The purpose of the paper is to introduce the Dynamic Phasor Modelling (DPM) approach for stability investigation and control design of single-phase Phase Locked Loops PLLs.
Asher, Greg +2 more
core +2 more sources