Results 201 to 210 of about 34,480 (263)

A Fast-Locking Digital Phase-Locked Loop

Third International Conference on Information Technology: New Generations (ITNG'06), 2006
A conventional digital phase-locked loop (DPLL) is designed using (Baker et al., 2003) to operate at 1GHz using 0.18 mum CMOS technology; its lock time is 4.19 mus. By adding a coarse/fine tuning control unit composed of a digital-to-analog converter (DAC) and a counter as well as switching the currents of the charge pump, a fast-locking DPLL results ...
Mahmoud Fawzy Wagdy, Srishti Vaishnava
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Lock Detection in Phase-Locked Loops

SIAM Journal on Applied Mathematics, 1992
The phase quadrature lock detector is used extensively to detect phase lock in phase-locked loops (PLLs). However, this lock detector's relationship to PLL closed-loop dynamics has never been established. A new theory is presented, which accomplishes this for a specified class of PLLs.
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Fast lock scheme for phase-locked loops

2009 IEEE Custom Integrated Circuits Conference, 2009
This paper describes a fast lock scheme for phaselocked loops (PLLs). The proposed scheme utilizes mostly digital logic and control to achieve significant reduction in PLL lock acquisition time, which enables dynamic power cycling for various sub-systems on SOC designs.
Amir Bashir, Jing Li, Kiran Ivatury, Naveed Khan, Nirav Gala, Noam Familia, Zulfiqar Mohammed   +6 more
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False Lock and Bifurcation in the Phase Locked Loop

SIAM Journal on Applied Mathematics, 1987
New results are given on the phenomenon of false lock in phase locked loops (PLL). First, it is proved that for small values of closed loop gain \(\delta\), there is only one function \(\omega_ f(\delta)\) which represents the frequency error in a false locked Type 1 PLL.
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Synchronizers based on carrier phase lock Loop and on symbol phase lock loop

2008 15th IEEE International Conference on Electronics, Circuits and Systems, 2008
The symbol synchronizer recoveries the clock and after, with it, samples and retimes the data. We present two synchronizer groups, the first based on filter with carrier phase lock loop (CPLL) and the second based on symbol phase lock loop (SPLL). Each group has four prototypes namely the analog, the hybrid, the combinational and the sequential.
Antonio D. Reis, José F. Rocha, Atílio Manuel da Silva Gameiro, José P. Carvalho   +3 more
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Concurrent separation of phase-locked and non-phase-locked activity

2022
Abstract Brain dynamics recorded via electroencephalography (EEG) is conceptualized as a sum of two components, “phase-locked” and “non-phase-locked” to the stimulus. Both activities are understood to be stemming from different neuronal mechanisms and hence accurately characterizing them is of immense importance in neuroscientific ...
Shubham Singhal, Priyanka Ghosh, Neeraj Kumar, Arpan Banerjee   +3 more
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Digital phase locked loop

ICASSP '78. IEEE International Conference on Acoustics, Speech, and Signal Processing, 2005
This paper deals with the design, construction and evaluation of a Digital Phase-Locked Loop. An exclusive OR gate serves as a linear phase detector. The integrator consists of a cascade of up/down decade counters. The D.C. value of each cycle from the phase detector is measured and accumulated. The rate of integration is determined by the clock input.
C. P. Reddy, Erik Fountain
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A low-noise and fast-locking phase-locked loop

Proceedings of the 2003 American Control Conference, 2003., 2002
In this article, a phase-locked loop (PLL) is introduced. The proposed PLL, denoted by NPLL, is similar to the standard PLL except that it incorporates a nonlinear element and a low-pass filter in its loop. It is shown that by appropriate choices of these two components, the NPLL outperforms the standard PLL in three respects: (i) it has a large ...
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Phase locking of ring lasers

Applied Optics, 1987
Phase locking of two CO/sub 2/ ring lasers is achieved by injecting the reverse mode output from each ring into the other through reverse mode clipper mirrors. (AIP)
S, Holswade, R, Riviere, K, Calahan, C, Clayton, C A, Huguley   +4 more
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Novel phase-locked loops with enhanced locking capabilities

Proceedings of the 2002 American Control Conference (IEEE Cat. No.CH37301), 2001
In the paper, a novel phase-locked loop (PLL) is introduced. The proposed PLL, denoted by NPLL, is similar to the standard PLL except that it incorporates a nonlinear element and a low pass filter in its loop. The NPLL outperforms the standard PLL: (i) it has a large acquisition range, i.e., it can achieve locking in situations where the standard PLL ...
openaire   +1 more source