Results 261 to 270 of about 148,748 (316)
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2003
The function of a PLL is to generate an output clock whose phase is locked to that of the input reference clock. In order to satisfy this condition, the output clock frequency either has to be equal to the input clock frequency or has to be a multiple of the input clock frequency, i.e.
Liang Dai, Ramesh Harjani
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The function of a PLL is to generate an output clock whose phase is locked to that of the input reference clock. In order to satisfy this condition, the output clock frequency either has to be equal to the input clock frequency or has to be a multiple of the input clock frequency, i.e.
Liang Dai, Ramesh Harjani
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A comparative study between Fractional-N PLL and Flying-Adder PLL
Proceedings of 2010 IEEE International Symposium on Circuits and Systems, 2010Frequency synthesis is one of the most important and most actively researched subjects in the field of VLSI mixed-signal circuit design. Among the existing techniques in this area, Fractional-N architecture is a widely used one for generating frequencies which are not integer multiple of the input reference frequency.
Liming Xiu, Chen-Wei Huang, Ping Gui
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Digital wireline and PLL techniques
2009 IEEE Custom Integrated Circuits Conference, 2009Trends in deeply-scaled CMOS technology motivate designers to carefully consider using more digital circuitry and digital control techniques for high-speed wireline transceivers and related building blocks. This session presents recent developments in the design and analysis of various digital approaches.
Gu-Yeon Wei, Afshin Momtaz
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14th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems, 2011
In this paper PLL Design tool, created in Matlab from MathWorks, has been presented. The tool allows to analyze loop stability and phase noise of PLL, based on phase-locked loop linear model. Fast evaluation of loop filter components values for popular passive and active filters is possible.
Krzysztof Siwiec +2 more
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In this paper PLL Design tool, created in Matlab from MathWorks, has been presented. The tool allows to analyze loop stability and phase noise of PLL, based on phase-locked loop linear model. Fast evaluation of loop filter components values for popular passive and active filters is possible.
Krzysztof Siwiec +2 more
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PLL system for harmonic analysis
2011 10th International Conference on Environment and Electrical Engineering, 2011PLL principles system and its applications in harmonic analysis are firstly discussed and then integrated presenting methods to increase the PLL-based instrumentation efficiency. A comparison between the performance of systems before and after the application of these methods are shown to validate the efficiency o f the proposed methods.
ANTONELLI A +2 more
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ESSCIRC Conference 2016: 42nd European Solid-State Circuits Conference, 2016
This paper compares the properties of traditional digital phase-locked loops based on multi-bit, high-resolution time-to-digital converters and those based on bang-bang phase detectors. Novel analysis is presented which show that bang-bang digital PLLs allow better phase noise and spur performance at lower power consumption, area and complexity.
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This paper compares the properties of traditional digital phase-locked loops based on multi-bit, high-resolution time-to-digital converters and those based on bang-bang phase detectors. Novel analysis is presented which show that bang-bang digital PLLs allow better phase noise and spur performance at lower power consumption, area and complexity.
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Hybrid PLL architectures and implementations
2018 IEEE Custom Integrated Circuits Conference (CICC), 2018SSCS Webinar ...
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The convergence of a PLL with variable parameters
International Journal of Circuit Theory and Applications, 1990AbstractA phase‐locked loop with variable parameters is considered. In such a system it is possible to obtain a short convergence time together with a small bandwidth. It is supposed that the PLL's parameters cannot be switched and there is a restriction on the velocity of the parameter variation.An optimal strategy of parameter variation is obtained ...
Dov Wulich, Moshe Bar
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Preparation of PLL-PEG-PLL and its application to DNA encapsulation
Science in China Series B: Chemistry, 2006PLL-PEG-PLL was synthesized by deprotection of the amino group of PLL(Z)-PEG-PLL(Z). The properties of the polyion complex (PIC) micelles comprising of PLL-PEG-PLL and DNA were investigated. The results showed that the core of PIC was formed by PLL and DNA through electrostatic interactions, and PEG was shell of PIC, so PIC micelles in aqueous medium ...
Zigang Yang +5 more
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Proceedings of IEEE East-West Design & Test Symposium (EWDTS'08), 2008
The purpose of this work is to add one more circuit into the traditional PLL to define the lock condition. Fully digital lock detector is presented. Presented circuit provides a simple design, process independence and design automation.
Vazgen Melikyan +3 more
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The purpose of this work is to add one more circuit into the traditional PLL to define the lock condition. Fully digital lock detector is presented. Presented circuit provides a simple design, process independence and design automation.
Vazgen Melikyan +3 more
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