Results 271 to 280 of about 148,748 (316)

Cascade three-phase PLL for unbalance and harmonic distortion operation (CSRF-PLL)

IECON 2014 - 40th Annual Conference of the IEEE Industrial Electronics Society, 2014
This paper presents a phase-locked loop (PLL) method aimed to provide an estimation of the phase angle and the amplitude of the fundamental positive sequence component of a three-phase reference signal subject to severe unbalance and high harmonic distortion. In addition the proposed scheme provides the estimation of the angular frequency, and both the
Gerardo Escobar, Carl Ngai Man Ho, Sami Pettersson, Manuel J. Lopez-Sanchez, Andres A. Valdez-Fernandez   +4 more
openaire   +1 more source

An Algorithm for Automatic Tuning of PLLs

2007 IEEE International Symposium on Circuits and Systems (ISCAS), 2007
In this paper we propose a new method for the automatic tuning of PLLs with switched capacitor banks in their VCOs. The method is implemented on a 7 GHz 130-nm CMOS PLL with 5 binary control bits. Measurement results are provided and analysis of the method is illustrated.
openaire   +1 more source

Equivocation as a Cause of PLL Hangup

IEEE Transactions on Communications, 1982
The role of phase equivocation in hangup of phase-lock loops is clarified. Equivocation can occur and lead to hangup if and only if the phase detector characteristic is discontinuous at the reverse-slope null.
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Dtc-based pll and method for operating the dtc-based pll

2018
The disclosure provides a phase locked loop, PLL, for phase locking an output signal to a reference signal. The PLL comprises a reference path providing the reference signal to a first input of a phase detector, a feedback loop providing the output signal of the PLL as a feedback signal to a second input of the phase detector, a controllable oscillator
Markulic, Nereo, Liu, Yao, Craninckx, Jan   +2 more
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Εφαρμογές PLL:

2009
Στο πρώτο κεφάλαιο γίνεται αναφορά στην έννοια του χάους και σύντομη ιστορική διαδρομή με βάση τους πρώτους θεωρητικούς επιστήμονες που ασχολήθηκαν με αυτό. Στην συνέχεια περιγράφονται τα δυναμικά κυκλώματα και η χαοτική συμπεριφορά των ηλεκτρικών κυκλωμάτων.
openaire   +1 more source

Observer-Controller Digital PLL

IEEE Transactions on Circuits and Systems I: Regular Papers, 2010
A digital phase-locked loop (DPLL) has been recently developed to exploit the increasing transistor speed of modern process technology. By employing a digitally controlled oscillator (DCO) and a time-to-digital converter (TDC), the loop filter of a DPLL becomes all-digital.
openaire   +1 more source

Noise Properties of PLL Systems

IEEE Transactions on Communications, 1982
This is a survey paper which begins by the derivation of the general PLL noise equation and by dividing the additive noises into the passband group and the stopband group. In the following paragraphs the behavior of all the major sources of additive noises is investigated and the practical numerical values of the respective power spectral densities are
openaire   +1 more source

Analog Techniques and PLLs

2007 IEEE International Solid-State Circuits Conference. Digest of Technical Papers, 2007
Vadim Gutnik, Stefan Heinen
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On-Chip Jitter Learning for PLL

IEEE Design & Test, 2022
Wei-Hao Chen, Shi-Yu Huang
openaire   +1 more source

Performance enhancement of DSOGI-PLL with a simple approach in grid-connected applications

Energy Reports, 2022
Fehmi Sevilmiş, Hulusi Karaca
exaly