Results 71 to 80 of about 35,601 (122)

PLL- and FLL-Based Speed Estimation Schemes for Speed-Sensorless Control of Induction Motor Drives: Review and New Attempts

IEEE transactions on power electronics, 2022
Phase-locked loops (PLLs) and frequency-locked loops (FLLs) are of importance in power and energy applications. Both technologies have been introduced to speed-sensorless- controlled motor drives, and increasing applications of PLLs and FLLs for speed ...
Huimin Wang, Yongheng Yang, X. Ge, Y. Zuo, Yan Yue, Songtao Li   +5 more
semanticscholar   +1 more source

Estimated Position Error Suppression Using Novel PLL for IPMSM Sensorless Drives Based on Full-Order SMO

IEEE transactions on power electronics, 2022
To heighten the position estimation accuracy of sensorless control of interior permanent magnet synchronous motor (IPMSM), an improved full-order sliding mode observer (FSMO) based on novel phase-locked loop (PLL) is proposed in this article. By contrast
Zhonggang Yin, Yanping Zhang, Xinping Cao, D. Yuan, Jing Liu   +4 more
semanticscholar   +1 more source

Generalized Swing Equation and Transient Synchronous Stability With PLL-Based VSC

IEEE transactions on energy conversion, 2022
With widespread application of voltage source converter (VSC) as a key energy-conversion power electronic device by using the phase-locked loop (PLL) technique for synchronization, the system dynamics has become much complicated.
Rui Ma, Jinxin Li, J. Kurths, Shi-jie Cheng, Mengyuan Zhan   +4 more
semanticscholar   +1 more source

Stability Analysis of the Grid-Connected Inverter Considering the Asymmetric Positive-Feedback Loops Introduced by the PLL in Weak Grids

IEEE transactions on industrial electronics (1982. Print), 2022
The stability of the grid-connected inverter (GCI) system in weak grids is deteriorated due to the asymmetric positive-feedback loops (APFLs) introduced by the phase-locked loop (PLL) structure.
Chunming Tu, Jiayuan Gao, Fan Xiao, Qi Guo, Fei Jiang   +4 more
semanticscholar   +1 more source

A Straightforward Quadrature Signal Generator for Single-Phase SOGI-PLL With Low Susceptibility to Grid Harmonics

IEEE transactions on industrial electronics (1982. Print), 2022
Suppressing the negative effects of grid voltage harmonics on the estimated frequency of a phase-locked loop (PLL) is a challenge in literature. This article proposes an easy-to-implement quadrature signal generator (QSG) to attenuate the oscillations on
S. Mohamadian, Hamidreza Pairo, A. Ghasemian   +2 more
semanticscholar   +1 more source

Modulation and Demodulation

Communication Systems Principles Using MATLAB®, 2018
This chapter discusses common types of modulation and their variants. It explores the spectral effects of modulation and explains why certain types of modulation are used in differing situations.
J. Leis
semanticscholar   +1 more source

A 12.5-GHz Fractional-N Type-I Sampling PLL Achieving 58-fs Integrated Jitter

IEEE Journal of Solid-State Circuits, 2022
This article presents a fractional-N sampling type-I phase-locked loop (PLL). To overcome the impairments of a conventional type-I PLL, namely the frequency-tuning-dependent time offset and the narrow range of the sampling phase detector (SPD), which ...
M. Mercandelli, Alessio Santiccioli, A. Parisi, L. Bertulessi, Dmytro Cherniak, A. Lacaita, C. Samori, S. Levantino   +7 more
semanticscholar   +1 more source

Impact of PLL Frequency Limiter on Synchronization Stability of Grid Feeding Converter

IEEE Transactions on Power Systems, 2022
It is well known that grid-feeding converters that synchronize to the grid through a Phase-Locked Loop (PLL) can become unstable after a fault. An often-neglected element that plays an important role in the converter synchronization stability is the PLL ...
Junru Chen, Muyang Liu, H. Geng, T. O’Donnell, F. Milano   +4 more
semanticscholar   +1 more source

A 25.8GHz Integer-N PLL With Time-Amplifying Phase-Frequency Detector Achieving 60fsrms Jitter, -252.8dB FoMJ, and Robust Lock Acquisition Performance

IEEE International Solid-State Circuits Conference, 2022
With the rapid development of the modern communication technology, the communication standards impose stringent performance requirements, such as the ultra-low jitter requirement, on the phase-locked-loop (PLL) frequency synthesizers.
Xinlin Geng, Yibo Tian, Yao Xiao, Zonglin Ye, Qian Xie, Zheng Wang   +5 more
semanticscholar   +1 more source

Extended State-Based OSG Configurations for SOGI PLL With an Enhanced Disturbance Rejection Capability

IEEE transactions on industry applications, 2022
Changes in the orthogonal signal generator (OSG) configuration of the standard second-order generalized integrator-based phase-locked loop (S-SOGI PLL) have shown to offer an improved low-voltage ride-through capability.
Abdullahi Bamigbade, V. Khadkikar
semanticscholar   +1 more source