Results 81 to 90 of about 35,601 (122)

A 14-nm Ultra-Low Jitter Fractional-N PLL Using a DTC Range Reduction Technique and a Reconfigurable Dual-Core VCO

IEEE Journal of Solid-State Circuits, 2021
This work presents a 6-GHz low-jitter and high figure-of-merit (FoM) fractional- $N$ phase-locked loop (PLL). It uses a digital-to-time converter (DTC)-based sampling PLL architecture.
Wanghua Wu, Chih-Wei Yao, Chengkai Guo, Pei-Yuan Chiang, Lei Chen, Pak-Kim Lau, Zhanjun Bai, S. Son, T. Cho   +8 more
semanticscholar   +1 more source

Position-Estimation Deviation-Suppression Technology of PMSM Combining Phase Self-Compensation SMO and Feed-Forward PLL

IEEE Journal of Emerging and Selected Topics in Power Electronics, 2021
The sensorless drive method of the permanent magnet synchronous motor (PMSM) has attracted wide attention for its low cost and high reliability. As a critical technology, a fast and high-precision rotor-position estimation is essential.
Gang Liu, Haifeng Zhang, Xinda Song
semanticscholar   +1 more source

Sensorless Predictive Control of SPMSM-Driven Light EV Drive Using Modified Speed Adaptive Super Twisting Sliding Mode Observer With MAF-PLL

IEEE Journal of Emerging and Selected Topics in Industrial Electronics, 2021
Sensor reduction is a key sought after requirement for a surface mounted permanent magnet synchronous motor (SPMSM) electric vehicle (EV) drive to improve reliability and to reduce its cost.
S. R, Bhim Singh
semanticscholar   +1 more source

A Type-3 Modified SOGI-PLL With Grid Disturbance Rejection Capability for Single-Phase Grid-Tied Converters

IEEE transactions on industry applications, 2021
This article presents a type-3 second-order generalized integrator phase-locked loop (SOGI-PLL) algorithm for single-phase system. Disturbances, such as dc offset and harmonics, are present in the practical grid voltages, due to occurrence of faults ...
S. Prakash, J. Singh, R. Behera, Arijit Mondal   +3 more
semanticscholar   +1 more source

A Harmonic-Mixing PLL Architecture for Millimeter-Wave Application

IEEE Journal of Solid-State Circuits, 2022
A low-noise synthesizer design in the millimeter-wave (mm-wave) range is complicated by the invariably large closed-loop gain and the high operation frequency of the voltage-controlled oscillator (VCO).
Dihang Yang, D. Murphy, H. Darabi, A. Behzad, A. Abidi, S. Au, Sraavan R. Mundlapudi, Kejian Shi, Weiyu Leng   +8 more
semanticscholar   +1 more source

Savitzky–Golay Filter-Based PLL: Modeling and Performance Validation

IEEE Transactions on Instrumentation and Measurement, 2022
A phase-locked loop (PLL) based on synchronous reference frame (SRF) is a standard PLL that has a simple construction and performs well under undisrupted grid conditions.
Kamrul Hasan, Sheikh Tanzim Meraj, Muhammad Murtadha Othman, M. S. Hossain Lipu, M. Hannan, K. Muttaqi   +5 more
semanticscholar   +1 more source

Influence of PLL on Stability of Interconnected Grid-Forming and Grid-Following Converters

IEEE transactions on power electronics
This letter analyzes the impact of a phase-locked loop (PLL) on small-signal stability in a system of interconnected grid-forming and grid-following (GFL) converters.
Yang Wu, Heng Wu, F. Zhao, Zejie Li, Xiongfei Wang   +4 more
semanticscholar   +1 more source

10.4 A 45.5fs-Integrated-Random-Jitter and -75dBc-Integer-Boundary-Spur BiCMOS Fractional-N PLL with Suppression of Fractional, Horn, and Wandering Spurs

IEEE International Solid-State Circuits Conference
Fractional-N PLLs are plagued by spurs that result from interaction between the shaped quantization noise introduced by the controller of the feedback divider and non-linearities in the loop.
Michael Peter Kennedy, Valerio Mazzaro, Stefano Tulisi, M. Scully, Niall McDermott, James Breslin   +5 more
semanticscholar   +1 more source

15.4 A 22nm 2Mb ReRAM Compute-in-Memory Macro with 121-28TOPS/W for Multibit MAC Computing for Tiny AI Edge Devices

IEEE International Solid-State Circuits Conference, 2020
Nonvolatile computing-in-memory (nvCIM) can improve the latency (tAC) and energy-efficiency (EFMAC) of tiny AI edge devices performing multiply-and-accumulate (MAC) computing after system wake-up.
Cheng-Xin Xue, Tsung-Yuan Huang, Je-Syu Liu, Ting-Wei Chang, Hui-Yao Kao, Jing-Hong Wang, Ta-Wei Liu, Shih-Ying Wei, Sheng-Po Huang, Wei-Chen Wei, Yi-Ren Chen, Tzu-Hsiang Hsu, Yen-Kai Chen, Yun-Chen Lo, Tai-Hsing Wen, C. Lo, Ren-Shuo Liu, C. Hsieh, K. Tang, Meng-Fan Chang   +19 more
semanticscholar   +1 more source

Grid-Synchronization Stability Analysis and Loop Shaping for PLL-Based Power Converters With Different Reactive Power Control

IEEE Transactions on Smart Grid, 2020
Power converters may lose synchronization with the remaining network when integrated in a weak power grid. Such an instability phenomenon [known as grid-synchronization instability (GSI)] features the frequency divergence of phase-locked loop (PLL) and ...
Linbin Huang, H. Xin, Zhiyi Li, P. Ju, Hui Yuan, Z. Lan, Zhen Wang   +6 more
semanticscholar   +1 more source