Results 251 to 260 of about 647,836 (310)

Structurally engineered heat loss suppression in nanogap-aligned nanowires for power efficient heating. [PDF]

open access: yesNanoscale Adv
Jo MS   +8 more
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The power consumption of Bluetooth scatternets

CCNC 2006. 2006 3rd IEEE Consumer Communications and Networking Conference, 2006., 2006
Low power has become a primary concern in the field of ad‐hoc and personal area networks. As manufacturers start endowing their designs with scatternet support, Bluetooth is emerging as a key enabling technology. Although this is driving research on Bluetooth power optimization, most proposals are based on over‐simplified, fully theoretical, or old and
Luca Negri, Jan Beutel, Matthias Dyer
openaire   +1 more source

Variations in CPU Power Consumption

Proceedings of the 7th ACM/SPEC on International Conference on Performance Engineering, 2016
Experimental analysis of computer systems' power consumption has become an integral part of system performance evaluation, efficiency management, and model-based analysis. As with all measurements, repeatability and reproducibility of power measurements are a major challenge.
Jóakim von Kistowski   +5 more
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Power Consumption Management on FPGAs

15th International Conference on Electronics, Communications and Computers (CONIELECOMP'05), 2005
During the last years, the number of hardware implementations based on field programmable gate arrays (FPGA) is increasing because it satisfies the high speed of system and hardware cost constraints. FPGA implementation allows the building of rapid prototypes reducing development times and board area.
Andrés David García García   +2 more
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ARM7TDMI power consumption

IEEE Micro, 1997
Portable and handheld products require processors that consume less power than those in desktop and other powered applications. As a result, designers must analyze power use in the early stage of design both at the circuit and system levels. RISC processors, such as our ARM7TDMI, have both strengths and weaknesses as far as power consumption is ...
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GATE RESIZING TO REDUCE POWER CONSUMPTION

International Journal of Foundations of Computer Science, 2002
We study the problem of resizing gates so as to reduce overall power consumption while satisfying a circuit's timing constraints. Polynomial time algorithms for series-parallel and tree circuits are obtained. Gate resizing with multigate modules is shown to be NP-hard.
Edward Y. C. Cheng, Sartaj Sahni
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Evaluation of power consumption in adiabatic circuits

2000 IEEE International Symposium on Circuits and Systems. Emerging Technologies for the 21st Century. Proceedings (IEEE Cat No.00CH36353), 2002
In this paper a simple and accurate model to evaluate the energy consumption of the digital adiabatic circuits is proposed. It is based on a linearization of the circuit, which leads to an RC mesh equivalent circuit. The obtained expression of the energy consumption of a generic adiabatic gate is very simple, thus it can be used for pencil-and-paper ...
M. ALIOTO, PALUMBO, Gaetano
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