Results 281 to 290 of about 25,214,365 (363)

Process Variation-Aware Test for Resistive Bridges [PDF]

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2009
This paper analyses the behaviour of resistive bridging faults under process variation and shows that process variation has a detrimental impact on test quality in the form of test escapes.
Bashir M Al-Hashimi, Saqib Khursheed, S M Reddy   +2 more
exaly   +2 more sources

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Process variation-aware approximate full adders for imprecision-tolerant applications

Computers & electrical engineering, 2020
In imprecision-tolerant applications such as multimedia and signal processing a slightly degraded output quality is acceptable, which could lead to significant power reduction. We have proposed three approximate full adders for such applications. We have
M. Mirzaei, S. Mohammadi
semanticscholar   +1 more source

A low power subthreshold Schmitt Trigger based 12T SRAM bit cell with process-variation-tolerant write-ability

Microelectronics Journal, 2020
Scaling of supply voltage is a well-received approach to reduce power consumption in Static Random Access Memory (SRAM). However, conventional 6T and 8T SRAMs suffer from degraded stability due to random process variations, thereby limiting voltage ...
Prakhar Sharma, Shourya Gupta, K. Gupta, N. Pandey   +3 more
semanticscholar   +1 more source

Process-variation Effects on 3D TLC Flash Reliability: Characterization and Mitigation Scheme

International Conference on Software Quality, Reliability and Security, 2020
In Solid State Drives, flash management techniques such as wear-leveling and refresh usually assume NAND flash memories have the same endurance value. However, the actual endurance values differ from blocks to blocks.
Yuqian Pan, Haichun Zhang, Mingyang Gong, Zhenglin Liu   +3 more
semanticscholar   +1 more source

A genomic mutational constraint map using variation in 76,156 human genomes

Nature, 2023
A genomic constraint map for the human genome constructed using data from 76,156 human genomes from the Genome Aggregation Database shows that non-coding constrained regions are enriched for regulatory elements and variants associated with complex ...
Siwei Chen, L. Francioli, J. Goodrich, Ryan L. Collins, M. Kanai, Qingbo S. Wang, Jessica Alföldi, N. Watts, C. Vittal, L. Gauthier, T. Poterba, Michael W. Wilson, Yekaterina Tarasova, W. Phu, R. Grant, Mary T. Yohannes, Zan Koenig, Y. Farjoun, E. Banks, S. Donnelly, Stacey Gabriel, N. Gupta, S. Ferriera, C. Tolonen, Sam Novod, L. Bergelson, David Roazen, Valentín Ruano-Rubio, Miguel Covarrubias, Christopher Llanwarne, Nikelle Petrillo, Gordon Wade, Thibault Jeandet, Ruchi Munshi, Kathleen M. Tibbetts, A. O’Donnell-Luria, M. Solomonson, C. Seed, Alicia R. Martin, M. Talkowski, Heidi L. Rehm, M. Daly, G. Tiao, B. Neale, D. MacArthur, K. Karczewski   +45 more
semanticscholar   +1 more source

Process Variations and Process-Tolerant Design

20th International Conference on VLSI Design held jointly with 6th International Conference on Embedded Systems (VLSID'07), 2007
While CMOS technology has served semiconductor industry marvelously (by allowing nearly exponential increase in performance and device integration density), it faces some major roadblocks at sub-90nm process nodes due to the intrinsic physical limitations of the devices.
Swarup Bhunia, Saibal Mukhopadhyay, Kaushik Roy 0001   +2 more
openaire   +1 more source

Minimizing Retention Induced Refresh Through Exploiting Process Variation of Flash Memory

IEEE transactions on computers, 2019
Refresh schemes have been the default approach in NAND flash memory to avoid data losses. The critical issue of the refresh schemes is that they introduce additional costs on lifetime and performance. Recent work proposed to minimize the refresh costs by
Yejia Di, Liang Shi, Congming Gao, Qiao Li, C. Xue, Kaijie Wu   +5 more
semanticscholar   +1 more source

Aging-Aware Workload Management on Embedded GPU Under Process Variation

IEEE transactions on computers, 2018
Graphics Processing Units (GPUs) have been employed in embedded systems to handle increased amounts of computation and to satisfy the timing requirement.
Haeseung Lee, M. Shafique, M. A. Al Faruque   +2 more
semanticscholar   +1 more source

Calibrating Process Variation at System Level with In-Situ Low-Precision Transfer Learning for Analog Neural Network Processors

Design Automation Conference, 2018
Process Variation (PV) may cause accuracy loss of the analog neural network (ANN) processors, and make it hard to be scaled down, as well as feasibility degrading. This paper first analyses the impact of PV on the performance of ANN chips.
Kaige Jia, Zheyu Liu, Qi Wei, F. Qiao, Xinjun Liu, Yi Yang, Hua Fan, Huazhong Yang   +7 more
semanticscholar   +1 more source

All-Digital Process-Variation-Calibrated Timing Generator for ATE With 1.95-ps Resolution and Maximum 1.2-GHz Test Rate

IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2018
In this paper, an all-digital process-variation-calibrated high-performance timing generator for an automatic test equipment is proposed. The proposed timing generator generates process-variation-tolerant variable delays for high and wide-range testing ...
Dong-Hoon Jung, Kyungho Ryu, Jung-Hyun Park, Seong-ook Jung   +3 more
semanticscholar   +1 more source