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Back-end porting of FT_MX based on LLVM compilation architecture [PDF]
MATEC Web of Conferences, 2021 The processor FT_MX is a high-performance chip independently developed by the National University of Defense Technology, with an innovative architecture and instruction set.
Deng Ping +3 more
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Early Prediction of DNN Activation Using Hierarchical Computations
Mathematics, 2021 Deep Neural Networks (DNNs) have set state-of-the-art performance numbers in diverse fields of electronics (computer vision, voice recognition), biology, bioinformatics, etc.
Bharathwaj Suresh +4 more
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IEEE Access, 2023 Edge computing is becoming increasingly popular in artificial intelligence (AI) application development due to the benefits of local execution. One widely used approach to overcome hardware limitations in edge computing is heterogeneous computing, which ...
Hyun Woo Oh, Seung Eun Lee
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Results in Physics, 2023 More physical qubits and qubit connections integrated on a superconducting quantum processor can improve the ability to execute quantum programs, but on the other hand, they might increase the probability of frequency collisions.
Tian Yang +5 more
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Energy Efficient Multi-Core Processing [PDF]
Electronics, 2014 This paper evaluates the present state of the art of energy-efficient embedded processor design techniques and demonstrates, how small, variable-architecture embedded processors may exploit a run-time minimal architectural synthesis technique to achieve ...
Charles Leech, Tom J. Kazmierski
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IEEE Access, 2022 This paper presents a high-performance and energy efficient processor exploiting a Magnetoresistive-based Computing-in-Memory array architecture (so-called MagCiM processor), to perform Boolean logic functions on operands stored in a memory array.
Vahid Jamshidi +2 more
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Idempotent processor architecture [PDF]
Proceedings of the 44th Annual IEEE/ACM International Symposium on Microarchitecture, 2011 Improving architectural energy efficiency is important to address diminishing energy efficiency gains from technology scaling. At the same time, limiting hardware complexity is also important. This paper presents a new processor architecture, the idempotent processor architecture, that advances both of these directions by presenting a new execution ...
Marc de Kruijf +1 more
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ALGORITHM OF RATIONAL PROCESSOR ARCHITECTURE [PDF]
Научно-технический вестник информационных технологий, механики и оптики, 2015 The paper deals with an algorithm that makes it possible to decide on processor architecture for computational kernel. This architecture provides the maximum possible rate of the computational process.
N. A. Zykov +2 more
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Hardware/software co-verification of USB3.0 IP core under PowerPC architecture
Dianzi Jishu Yingyong, 2022 With the increasing requirement of transmission rate of USB,the traditional PowerPC processor based on the USB2.0 can not meeet the requirements of high speed and large-capacity transmission.The paper presents a solution of USB 3.0 base on PowerPC ...
Deng Jiawei +4 more
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Project design for computer architecture practical sessions based on field-programmable gate array
Mokslas: Lietuvos Ateitis, 2021 Field-programmable logic arrays are often used in courses on computer architecture. The student must describe the processor with the external components necessary for its operation in the specified HDL (hardware description language) language according ...
Kęstutis Bartnykas
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