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Pipeline quantum processor architecture for silicon spin qubits [PDF]
npj Quantum Information, 2023 We propose a quantum processor architecture, the qubit ‘pipeline’, in which run-time scales additively as functions of circuit depth and run repetitions. Run-time control is applied globally, reducing the complexity of control and interconnect resources.
S. M. Patomäki +5 more
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Trends in Processor Architecture [PDF]
Harnessing Performance Variability in Embedded and High-performance Many/Multi-core Platforms, 2018 This paper presents an overview of the main trends in processor architecture. It starts with an analysis of the past evolution of processors and the main driving forces behind it, and then it focuses on a description of the main architectural features of current processors.
Antonio González
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Idempotent processor architecture [PDF]
Proceedings of the 44th Annual IEEE/ACM International Symposium on Microarchitecture, 2011 Improving architectural energy efficiency is important to address diminishing energy efficiency gains from technology scaling. At the same time, limiting hardware complexity is also important. This paper presents a new processor architecture, the idempotent processor architecture, that advances both of these directions by presenting a new execution ...
Marc de Kruijf +1 more
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Architecture validation for processors [PDF]
ACM SIGARCH Computer Architecture News, 1995 Modem, high performance microprocessors are extremely complex machines which require substantial validation effort to ensure functional correctness prior to tapeout. Generating the corner cases to test these designs is a mostly manual process, where completion is hard to judge.
Richard C. Ho +3 more
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An architecture of a dataflow single chip processor [PDF]
The 16th Annual International Symposium on Computer Architecture, 1989 A highly parallel (more than a thousand) dataflow machine EM-4 is now under development. The EM-4 design principle is to construct a high performance computer using a compact architecture by overcoming several defects of dataflow machines.
Shuichi Sakai +4 more
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Back-end porting of FT_MX based on LLVM compilation architecture [PDF]
MATEC Web of Conferences, 2021 The processor FT_MX is a high-performance chip independently developed by the National University of Defense Technology, with an innovative architecture and instruction set.
Deng Ping +3 more
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Microelectronics: Processor architectures II
Microprocessing and Microprogramming, 1988 Daniel Tabak
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Early Prediction of DNN Activation Using Hierarchical Computations
Mathematics, 2021 Deep Neural Networks (DNNs) have set state-of-the-art performance numbers in diverse fields of electronics (computer vision, voice recognition), biology, bioinformatics, etc.
Bharathwaj Suresh +4 more
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IEEE Access, 2023 Edge computing is becoming increasingly popular in artificial intelligence (AI) application development due to the benefits of local execution. One widely used approach to overcome hardware limitations in edge computing is heterogeneous computing, which ...
Hyun Woo Oh, Seung Eun Lee
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Persistent Processor Architecture
Micro, 2023 This paper presents PPA (Persistent Processor Architecture), simple microarchitectural support for lightweight yet performant whole-system persistence. PPA offers fully transparent crash consistency to all sorts of program covering the entire computing ...
Jianping Zeng +2 more
semanticscholar +1 more source