Results 251 to 260 of about 43,734 (318)

Inter-Channel Error Calibration Method for Real-Time DBF-SAR System Based on FPGA. [PDF]

open access: yesSensors (Basel)
Meng Y   +7 more
europepmc   +1 more source

History Directed Processor Architecture

open access: yesHistory Directed Processor Architecture
openaire  

Processor architecture

Proceedings of the 15th international conference on Parallel architectures and compilation techniques, 2006
CPUs and GPUs have evolved considerably in the past few years, and the pace of change and evolution in processor architecture is likely to increase. Constraints of excess heat dissipation and power consumption have forced a radical rethinking of microprocessor architecture, from the headlong pursuit of GHz clock rates to multicore and multithreaded ...
openaire   +1 more source

Multimedia processor architecture

Proceedings. IEEE International Conference on Multimedia Computing and Systems (Cat. No.98TB100241), 2002
The paper describes trends in the development of multimedia processor architecture that may be predicted on the basis of the availability of an ASIC with 10s of millions of gates. Multimedia processing based upon multi granular parallelism for diverse media needs supercomputing power for multi threaded, process level execution. Due to the appearance of
T. Ikedo, W.L. Martens
openaire   +1 more source

Array Processor Architecture

Computer, 1981
Today's array processors provide a cost-effective tool for increasing the speed at which highly computation-bound processing jobs can be carried out. They are maturing and expanding with greatly improved hardware and software—improvements that are primarily a result of the accumulated experience of the vendors and users of these machines.
openaire   +1 more source

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