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Embedded Processor Architectures

2021
Improvements in semiconductor technology enabled smaller feature sizes, better clock speeds, and high performance. Improvements in computer architectures were enabled by RISC architectures and efficient high-level language compilers. Together, we have enabled customized computer architectures from system-on-hips to powerful GPUs and high-performance ...
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Multithreaded processor architectures

IEEE Spectrum, 1995
The authors describe how independent streams of instructions, interwoven on a single processor, fill its otherwise idle cycles and so boost its performance. They detail how such multithreaded architectures take the tack of hiding latency by supporting multiple concurrent streams of execution.
G.T. Byrd, M.A. Holliday
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Reconfigurable processor architectures

Microprocessors and Microsystems, 1996
Abstract No particular application is well-supported by a conventional microprocessor which has a pre-determined set of functional units. This is particularly true in highly dynamic areas, such as multimedia, communications and other embedded systems.
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The Scalable Processor Architecture (SPARC)

Digest of Papers. COMPCON Spring 88 Thirty-Third IEEE Computer Society International Conference, 1988
An introduction is given to the SPARC architecture and its more interesting features. The discussion covers the registers (both window and floating-point), and instructions, including formats, load/store, integer computation, control transfer, floating-point computation, and coprocessor.
R.B. Garner   +11 more
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VLSI Processor Architecture

IEEE Transactions on Computers, 1984
A processor architecture attempts to compromise between the needs of programs hosted on the architecture and the performance attainable in implementing the architecture. The needs of programs are most accurately reflected by the dynamic use of the instruction set as the target for a high level language compiler.
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IBM Power9 Processor Architecture

IEEE Micro, 2017
The IBM Power9 processor has an enhanced core and chip architecture that provides superior thread performance and higher throughput. The core and chip architectures are optimized for emerging workloads to support the needs of next-generation computing. Multiple variants of silicon target the scale-out and scale-up markets.
Satish Kumar Sadasivam   +3 more
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Array-processor Architecture

1989
In his Turing Lecture entitled “Can Programming be Liberated from the von Neumann Style”, Backus [Bac78] introduced the term von Neumann bottleneck. This refers to the fundamental speed limitation of machines which have physically separate processing and storage units.
R. N. Ibbett, N. P. Topham
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The superthreaded processor architecture

IEEE Transactions on Computers, 1999
The common single-threaded execution model limits processors to exploiting only the relatively small amount of instruction-level parallelism that is available in application programs. The superthreaded processor, on the other hand, is a concurrent multithreaded architecture (CMA) that can exploit the multiple granularities of parallelism that are ...
null Jenn-Yuan Tsai   +4 more
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Advanced Processor Architecture

1998
Having read of the many advanced radar techniques in the offing, processor architecture may seem of little import. But the fact is that most of the advanced capabilities of airborne radars to date have only been made practical by substantial increases in digital processing throughput.
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Customizable embedded processor architectures

Euromicro Symposium on Digital System Design, 2003. Proceedings., 2003
In this paper, we present a framework for dynamic application customization for high-performance and low-power embedded processors. The proposed architecture is capable of utilizing application information to boost the performance and lower the power consumption of the most important microarchitectural components such as instruction/data caches and the
P. Petrov, A. Orailoglu
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