Results 281 to 290 of about 18,777,208 (356)

Multithreaded processor architectures

IEEE Spectrum, 1995
The authors describe how independent streams of instructions, interwoven on a single processor, fill its otherwise idle cycles and so boost its performance. They detail how such multithreaded architectures take the tack of hiding latency by supporting multiple concurrent streams of execution.
Mark A. Holliday, Gregory T. Byrd
openaire   +2 more sources

The superthreaded processor architecture

IEEE Transactions on Computers, 1999
The common single-threaded execution model limits processors to exploiting only the relatively small amount of instruction-level parallelism that is available in application programs. The superthreaded processor, on the other hand, is a concurrent multithreaded architecture (CMA) that can exploit the multiple granularities of parallelism that are ...
C. Amlo, David J. Lilja, Jian Huang, Pen-Chung Yew, Jenn-Yuan Tsai   +4 more
openaire   +2 more sources

A Configurable Cloud-Scale DNN Processor for Real-Time AI

International Symposium on Computer Architecture, 2018
Interactive AI-powered services require low-latency evaluation of deep neural network (DNN) models—aka ""real-time AI"". The growing demand for computationally expensive, state-of-the-art DNNs, coupled with diminishing performance gains of general ...
J. Fowers, Kalin Ovtcharov, Michael Papamichael, Todd Massengill, Ming Liu, Daniel Lo, Shlomi Alkalay, M. Haselman, Logan Adams, Mahdi Ghandi, Stephen Heil, Prerak Patel, Adam Sapek, Gabriel Weisz, Lisa Woods, S. Lanka, Steven K. Reinhardt, Adrian M. Caulfield, Eric S. Chung, Doug Burger   +19 more
semanticscholar   +1 more source

The Cell Processor Architecture

38th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO'05), 2006
This talk will present the Cell processor, jointly developed by the STI (Sony-Toshiba-IBM) partnership. Cell is a non-homogeneous chip multiprocessor intended for general-purpose applications but with a particular emphasis on multimedia performance. The Cell processor combines a 64bit Power Architecture(TM) core with 8 Synergistic Processors.
openaire   +2 more sources

Towards Nanoelectronics Processor Architectures [PDF]

Journal of Electronic Testing, 2007
In this paper, we focus on reliability, one of the most fundamental and important challenges, in the nanoelectronics environment. For a processor architecture based on the unreliable nanoelectronic devices, fault tolerance schemes are required so as to ensure the basic correctness of any computation.
Wenjing Rao, Alex Orailoglu, Ramesh Karri   +2 more
openaire   +1 more source

VLSI Processor Architecture

IEEE Transactions on Computers, 1984
A processor architecture attempts to compromise between the needs of programs hosted on the architecture and the performance attainable in implementing the architecture. The needs of programs are most accurately reflected by the dynamic use of the instruction set as the target for a high level language compiler.
openaire   +2 more sources

Manycore processor architectures

2019
Trade-offs between performance and power have dominated the processor architecture landscape in recent times and are expected to exert a considerable influence in the future. Processing technologies ceased to provide automatic speedups across generations, leading to the reliance on architectural innovation for achieving better performance.
Prasenjit Chakraborty, Bharath Narasimha Swamy, Preeti Ranjan Panda   +2 more
openaire   +2 more sources

The Scalable Processor Architecture (SPARC)

Digest of Papers. COMPCON Spring 88 Thirty-Third IEEE Computer Society International Conference, 1988
An introduction is given to the SPARC architecture and its more interesting features. The discussion covers the registers (both window and floating-point), and instructions, including formats, load/store, integer computation, control transfer, floating-point computation, and coprocessor.
R.B. Garner, A. Agrawal, David A. Patterson, Steve Kleiman, F. Briggs, B. Joy, D. Hough, E.W. Brown, R. Tuck, J. Pendleton, S. Muchnick, M. Namjoo   +11 more
openaire   +2 more sources

An overview of the mesa processor architecture

ACM SIGPLAN Notices, 1982
This paper provides an overview of the architecture of the Mesa processor, an architecture which was designed to support the Mesa programming system [4]. Mesa is a high level systems programming language and associated tools designed to support the development of large information processing applications (on the order of one million source lines ...
John D. Wick, Richard K. Johnsson
openaire   +2 more sources

The Architecture of the MU5 Processor

1979
The design of the MU5 processor was approached through its order code, this being the natural interface between software requirements and hardware organisation. Full interplay between the two aspects was considered vital throughout the design. Efficient processing of high-level language programs was the prime target. In ‘number crunching’ applications,
Derrick Morris, Roland N. Ibbett
openaire   +2 more sources