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A moving threads processor architecture MTPA
The Journal of Supercomputing, 2011Moving threads is a new kind of approach for multicore processor architectures. Traditionally, each thread stays in the core where it is created, and data is moved from the main memory via caches to each core and thread. In the moving threads approach, each core can access only a certain portion of the main memory via its local memory block, and thus ...
Martti Forsell, Ville Leppänen
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1989
In his Turing Lecture entitled “Can Programming be Liberated from the von Neumann Style”, Backus [Bac78] introduced the term von Neumann bottleneck. This refers to the fundamental speed limitation of machines which have physically separate processing and storage units.
Roland N. Ibbett, Nigel Topham
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In his Turing Lecture entitled “Can Programming be Liberated from the von Neumann Style”, Backus [Bac78] introduced the term von Neumann bottleneck. This refers to the fundamental speed limitation of machines which have physically separate processing and storage units.
Roland N. Ibbett, Nigel Topham
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Processor Architectures for Multimedia
1998In this chapter, we present contemporary VLSI processor architectures that support multimedia applications. We classified these processors into two groups: dedicated multimedia processors, which perform dedicated multimedia functions, such as MPEG encoding or decoding, and general-purpose processors that provide support for multimedia.
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Computer, 1982
Novel VLSI processor architectures, some implemented by only a few different types of simple cells, are leading the way towards a new generation of computers. A brief survey of these novel VLSI processor architectures illustrates the exciting work going on in the area, most of which is still at the research stage. 45 references.
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Novel VLSI processor architectures, some implemented by only a few different types of simple cells, are leading the way towards a new generation of computers. A brief survey of these novel VLSI processor architectures illustrates the exciting work going on in the area, most of which is still at the research stage. 45 references.
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Reconfigurable transputer processor architectures [PDF]
[1989] Proceedings of the Twenty-Second Annual Hawaii International Conference on System Sciences. Volume 1: Architecture Track, 2003 The author describes concurrent-processing computers capable of performance in the gigaflop (billions of floating-point operators) range on real scientific and engineering applications, which have ben developed as part of Esprit project 805. The architecture is readily scalable up to over a thousand processors and provides genuinely cost-effective ...
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Advanced Processor Architecture
1998Having read of the many advanced radar techniques in the offing, processor architecture may seem of little import. But the fact is that most of the advanced capabilities of airborne radars to date have only been made practical by substantial increases in digital processing throughput.
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Reconfigurable processor architectures
Microprocessors and Microsystems, 1996Abstract No particular application is well-supported by a conventional microprocessor which has a pre-determined set of functional units. This is particularly true in highly dynamic areas, such as multimedia, communications and other embedded systems.
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Processor architecture and data buffering
IEEE Transactions on Computers, 1992The tradeoff between visualizing or hiding the highest levels of the memory hierarchy, which impacts both performance and scalability, is examined by comparing a set of architectures from three major architecture families: stack, register, and memory-to-memory. The stack architecture is used as reference. It is shown that scalable architectures require
Mulder, H. (author) +1 more
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Architecture of a message-driven processor
Proceedings of the 14th annual international symposium on Computer architecture - ISCA '87, 1987We propose a machine architecture for a high-performance processing node for a message-passing, MIMD concurrent computer. The principal mechanisms for attaining this goal are the direct execution and buffering of messages and a memory-based architecture that permits very fast context switches.
Scott Wills +8 more
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A Reconfigurable Processor Architecture
2002Until now, the lack of software and hardware compatibility between existing reconfigurable processors make them less competitive with hard-wired processors for mainstream computing. In this paper we propose a reconfigurable processor architecture based on the von-Neumann computing model, so that software compatibility can be achieved with minimal work.
Hans Christoph Zeidler +2 more
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