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The Importance of Processor Architecture [PDF]

, 1990
Current-day multiprocessors represent the general belief that processor architecture is of little importance in designing parallel machines. In this Chapter, the fallacy of this assumption will be demonstrated on the basis of the two fundamental issue of latency and synchronization.
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The Expression Processor: A Pipelined, Multiple- Processor Architecture

IEEE Transactions on Computers, 1981
A nem multiple-processor architecture is described that can exploit the instruction level concurrency in numerical processing tasks. The expression processor contains multiple processing elements (PE's), which can be configured either as an SIMD [8] array or as an expression tree pipeline.
Zick, VanAken
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A reconfigurable parallel architecture for a fuzzy processor

Information Sciences, 1996
The spread of applications developed using fuzzy logic has stimulated research in the field of hardware architectures to provide adequate support for soft computing. The paper presents the design of a VLSI fuzzy processor whose main features are parallelism and reconfigurability.
ASCIA, Giuseppe, CATANIA, Vincenzo, Puliafito A, Vita L.   +3 more
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Processor architecture model for fuzzy control

Proceedings of Tenth International Symposium on Intelligent Control, 2002
The architecture of a fuzzy processor intended for high-speed control applications is described. Its main advantage is the inference speed that does not depend on the numer of used inputs and rules. This is accomplished by the usage of content addressable memory as a rule set storage.
Danko Basch, Mario Zagar
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Architecture of a Graphics Processor

[1992] Proceedings the 19th Annual International Symposium on Computer Architecture, 2005
The design principles that were applied in the design of the integer-RISC machine, are applied to the design of the Reduced Instruction Set Graphics Processor. The processor instruction is defined after critical evaluation of the common graphics operations.
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Design of Processor Arrays for Reconfigurable Architectures

The Journal of Supercomputing, 2001
zbMATH Open Web Interface contents unavailable due to conflicting licenses.
Renate Merker, Dirk Fimmel
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Architecture of a massively parallel processor

25 years of the international symposia on Computer architecture (selected papers), 1980
The massively parallel processor (MPP) system is designed to process satellite imagery at high rates. A large number (16,384) of processing elements (PE's) are configured in a square array. For optimum performance on operands of arbitrary length, processing is performed in a bit-serial manner.
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APRIL

Proceedings of the 17th annual international symposium on Computer Architecture - ISCA '90, 1990
Processors in large-scale multiprocessors must be able to tolerate large communication latencies and synchronization delays. This paper describes the architecture of a rapid-context-switching processor called APRIL with support for fine-grain threads and synchronization.
Beng-Hong Lim, John Kubiatowicz, David M. Kranz, Anant Agarwal   +3 more
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Architecture of a graphics processor (abstract)

ACM SIGARCH Computer Architecture News, 1992
The design principles that were applied in the design of the integer-RISC machine, are applied to the design of the Reduced Instruction Set Graphics Processor. The processor instruction is defined after critical evaluation of the common graphics operations.
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The Coherent Processor: an associative processor architecture and applications

COMPCON Spring '91 Digest of Papers, 2002
The Coherent Processor (CP), a massively parallel computer based on content addressable memory, is discussed. The CP offers advantages such as high performance, low cost, low weight, low power consumption, and a simple system interface and programming model. These features make it well-suited for real-time and embedded systems.
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