Results 31 to 40 of about 18,777,208 (356)
Word-serial unified and scalable semi-systolic processor for field multiplication and squaring
Alexandria Engineering Journal, 2021 This paper exhibits a word-serial unified and scalable semi-systolic processor core for concurrently executing both multiplication and squaring operations over GF(2k).
Atef Ibrahim
doaj +1 more source
Emerging Science Journal, 2017 Processors are main part of the calculation and decision making of a system. Today, due to the increasing need of industry and technology to faster and more accurate computing power, design and manufacture of parallel processing units, has been very much
Ali Hadizadeh, Ehsan Tanghatari
doaj +1 more source
Processors Allocation for MPSoCs With Single ISA Heterogeneous Multi-Core Architecture
IEEE Access, 2017 Single-instruction set architecture (ISA) heterogeneous multi-processor architecture is promising for developing multi-processor system-on-chips (MPSoCs). In this architecture, all processors execute the same instruction set, yet with various performance
Yi-Jung Chen +5 more
doaj +1 more source
FPGA Implementation of a CORDIC-Based Joint Angle Processor for a Climbing Robot
International Journal of Advanced Robotic Systems, 2013 This paper presents a novel architecture of a joint angle processor for a robot arm. The objective of the proposed coordinate, rotation, digital computer (CORDIC)-based joint angle processor is to provide a hardware solution for computing the inverse ...
Ying-Shen Juang +3 more
doaj +1 more source
Median and Morphological Specialized Processors for a Real-Time Image Data Processing
EURASIP Journal on Advances in Signal Processing, 2002 This paper presents the considerations on selecting a multiprocessor MISD architecture for fast implementation of the vision image processing. Using the author′s earlier experience with real-time systems, implementing of specialized hardware ...
Wiatr Kazimierz
doaj +1 more source
Run-Time Reconfigurable MPSoC-Based On-Board Processor for Vision-Based Space Navigation
IEEE Access, 2020 This paper describes a reconfigurable architecture for an on-board processor to be used in space exploration critical systems. It relies on, a dynamically reconfigurable multi-accelerator hardware architecture that provides transparent reconfiguration ...
Arturo Perez +6 more
doaj +1 more source
International Journal of Reconfigurable Computing, 2012 One of the most important steps in spectral analysis is filtering, where window functions are generally used to design filters. In this paper, we modify the existing architecture for realizing the window functions using CORDIC processor.
Supriya Aggarwal, Kavita Khare
doaj +1 more source
Evolutionary interplay between viruses and R‐loops
FEBS Letters, EarlyView.Viruses interact with specialized nucleic acid structures called R‐loops to influence host transcription, epigenetic states, latency, and immune evasion. This Perspective examines the roles of R‐loops in viral replication, integration, and silencing, and how viruses co‐opt or avoid these structures.
Zsolt Karányi +4 more
wiley +1 more source
Research and design of parallel architecture processor for elliptic curve cryptography
Tongxin xuebao, 2011 Based on the analysis of the ECC algorithms processing structure characteristics and parallel schedule on finite field level,a parallel architecture processor model for ECC was proposed which adopting the ILP and DLP.A prototype has been implemented ...
YANG Xiao-hui +3 more
doaj +2 more sources
Implementation of Middleware Switch ASIC Processor [PDF]
Telfor Journal, 2012 The new spacecraft area network (SCAN) system for internal satellite communication provides data transfer between different satellite components. The satellite components have their own communication protocols, which are translated by middleware (MW ...
S. Montenegro +3 more
doaj