Results 121 to 130 of about 15,659 (313)
Cooperative Technique Based on Sensor Selection in Wireless Sensor Network
An energy efficient cooperative technique is proposed for the IEEE 1451 based Wireless Sensor Networks. Selected numbers of Wireless Transducer Interface Modules (WTIMs) are used to form a Multiple Input Single Output (MISO) structure wirelessly ...
ISLAM, M. R., KIM, J.
doaj +1 more source
Matrix Manipulation Algorithms for Hasse Processor Implementation
– The processor is implemented in softwarehardware modules, which are based on the use of programming languages: C ++, Verilog, Python 2.7 and platforms: Microsoft Windows, X Window (in Unix and Linux) and Macintosh OS X. HDL-code generator makes it
Dahiri Farid, Hahanov, V. I.
core
Rapid single-chip secure processor prototyping on the Open SPARC FPGA platform
Secure processors have become increasingly important for trustworthy computing as security breaches escalate. By providing hardware-level protection, a secure processor ensures a safe computing environment where confidential data and applications can be ...
King Chan +15 more
core +1 more source
Radiotherapy (RT) response depends on the DNA repair capacity of tumor and host cells. We show that circulating tumor cell (CTC) counts and apoptosis rates before and after RT predict treatment response and outcome, which can be accessed via easily accessible liquid biopsy approaches. Created in BioRender. Wikman, H.
Yvonne Goy +10 more
wiley +1 more source
A data base processor semantics specification package
A Semantics Specification Package (DBPSSP) for the Intel Data Base Processor (DBP) is defined. DBPSSP serves as a collection of cross assembly tools that allow the analyst to assemble request blocks on the host computer for passage to the DBP.
Fishwick, P. A.
core
The Torus: An Exercise in Constructing a Processing Surface [PDF]
A "Processing Surface" is defined as a large, dense, and regular arrangement of processor and storage modules on a two-dimensional surface, e.g. a VLSI chip.
Martin, Alain J.
core
A video signal processor for mimd multiprocessing
The video signal processor AxPe1280V has been developed for implementation of different video coding applications according to standards like ITU-T H.261/H.263, and ISO MPEG-1/2.
Peter Pirsch +4 more
core +1 more source
This study shows that lung adenocarcinomas exploit developmental branching morphogenesis to acquire a therapy resistant basal‐like tumour cell state. This process was found to be regulated by combined TP53 loss‐of‐function and type‐I interferon signalling, identifying a novel axis for biomarker and therapeutic target discovery.
Kamila J Bienkowska +13 more
wiley +1 more source
This study investigates the efficiency of a multi-walled carbon nanotube-infused lauric acid (MWCNT-LA) heatsink with U-tube heat pipes filled with n-pentane for electronic processor cooling.
S. Kalaiselvam +2 more
doaj +1 more source
A module-based cell processor simulator
An interesting design alternative to replication-based chip multiprocessors is to create heterogeneous chip multiprocessors composed of several different cores, with one or more of them running the operating system and orchestrating execution, and the others serving as accelerators where parts of the application are off-loaded.
Cabarcas Jaramillo, Felipe +5 more
openaire +1 more source

