Results 21 to 30 of about 15,659 (313)
Extending systems-on-chip to the third dimension : performance, cost and technological tradeoffs. [PDF]
, 2007 Because of the today's market demand for high-performance, high-density portable hand-held applications, electronic system design technology has shifted the focus from 2-D planar SoC single-chip solutions to different alternative options as tiled silicon
Tenhunen, Hannu +8 more
core +1 more source
Research and Design of Five-Stage Pipelined RISC-V Microprocessor [PDF]
Jisuanji gongchengTo meet the requirements of low-overhead and high-performance applications in the embedded field, a 32 bit microprocessor based on the RISC-V open-source instruction set architecture has been developed.
Xuezhen ZHANG, Xihu WANG, Siwan DONG, Yihong ZHANG
doaj +1 more source
Instruction-level Real-time Secure Processor Using an Error Correction Code
Advances in Electrical and Computer Engineering, 2015 In this paper, we present a processor that detects security-attacks at the instruction level by checking the integrity of instructions in real time. To confirm the integrity of the instructions, we generate a parity chain of instructions and check them
YOON, S. M. +3 more
doaj +1 more source
Design and Implementation of ICP Fibre Channel Interface Board in IMA System [PDF]
Jisuanji gongcheng, 2016 To improve the information interaction ability of the Integrated Core Processor(ICP) in Integrated Modular Avionics(IMA) system and achieve the goal of Fibre Channel(FC) unified avionics network,ICP’s FC network interface card based on Field Programmable
WANG Yong,LI Bingqian,LIU Da
doaj +1 more source
2-D and 3-D Integration of Heterogeneous Electronic Systems under Cost, Performance and Technological Constraints [PDF]
, 2009 —Present day market demand for high-performance high-density portable hand-held applications has shifted the focus from 2-D planar system-on-a-chip-type single-chip solutions to al-ternatives such as tiled silicon and single-level embedded modules as ...
Pamunuwa, D. +13 more
core +1 more source
Implementing RLWE-based Schemes Using an RSA Co-Processor
Transactions on Cryptographic Hardware and Embedded Systems, 2018 We repurpose existing RSA/ECC co-processors for (ideal) lattice-based cryptography by exploiting the availability of fast long integer multiplication.
Martin R. Albrecht +5 more
doaj +1 more source
A Design Support Tool Set for Interface Circuits Between Synchronous and Asynchronous Modules
IEEE Access, 2023 In this paper, we propose a design support tool set for interface circuits between synchronous and asynchronous modules. To facilitate the design of interface circuits between synchronous and asynchronous modules, the proposed tool set generates ...
Shogo Semba, Hiroshi Saito
doaj +1 more source
Clock-modulation based watermark for protection of embedded processors [PDF]
Design, Automation & Test in Europe Conference & Exhibition (DATE), 2014, 2014 This paper presents a novel watermark generation technique for the protection of embedded processors. In previous work, a load circuit is used to generate detectable watermark patterns in the ASIC power supply. This approach leads to hardware area overheads.
Kufel, Jedrzej +5 more
openaire +4 more sources
Pediatric Blood &Cancer, EarlyView.ABSTRACT Pediatric gastroenteropancreatic neuroendocrine neoplasms (GEP‐NENs) are extremely rare and clinically heterogeneous. Management has largely been extrapolated from adult practice. This European Standard Clinical Practice Guideline (ESCP), developed by the EXPeRT network in collaboration with adult NEN experts, provides (adult) evidence ...
Michaela Kuhlen +23 more
wiley +1 more source