Results 31 to 40 of about 29,520 (201)

A 38.64-Gb/s Large-CPM 2-KB LDPC Decoder Implementation for nand Flash Memories

IEEE Open Journal of Circuits and Systems, 2022
The routing congestion over a QC-LDPC decoder with a large circular permutation matrix (CPM) size has long been an obstacle to high throughput designs.
Li-Wei Liu, Mu-Hua Yuan, Yen-Chin Liao, Hsie-Chia Chang   +3 more
doaj   +1 more source

LDPC Decoder of High Speed Multi-Rate DVB-S2 Based on FPGA

Xibei Gongye Daxue Xuebao, 2019
A multi-rate LDPC decoder architecture for DVB-S2 codes based on FPGA is proposed. Through elementary transformation on the parity check matrices of DVB-S2 LDPC codes, a new matrix whose left is a QC sub-matrix and right is Transformation of Staircase ...

doaj   +1 more source

Novel construction of QC-LDPC codes with modified 2-D GRS codes

Tongxin xuebao, 2015
The construction method for QC-LDPC (quasi-cyclic low density parity-check) code with modified two-dimensional generalized reed-solomon (2-D GRS) code is proposed using the generator polynomial of GRS code,so thus the constructed code can have better ...
Ming ZHAO, Xiao-lin ZHANG
doaj   +2 more sources

Analysis of Minimal LDPC Decoder System on a Chip Implementation [PDF]

, 2015
This paper presents a practical method of potential replacement of several different Quasi-Cyclic Low-Density Parity-Check (QC-LDPC) codes with one, with the intention of saving as much memory as required to implement the LDPC encoder and decoder in a ...
Dobos, J., Farkas, P., Palenik, T., Rakus, M.   +3 more
core   +2 more sources

Hierarchical and High-Girth QC LDPC Codes

, 2011
We present a general approach to designing capacity-approaching high-girth low-density parity-check (LDPC) codes that are friendly to hardware implementation.
Draper, Stark C., Wang, Yige, Yedidia, Jonathan S.   +2 more
core   +2 more sources

A Flexible NTT-Based Multiplier for Post-Quantum Cryptography

IEEE Access, 2023
In this work an NTT-based (Number Theoretic Transform) multiplier for code-based Post-Quantum Cryptography (PQC) is presented, supporting Quasi Cyclic Low/Moderate-Density Parity-Check (QC LDPC/MDPC) codes.
Kristjane Koleci, Paolo Mazzetti, Maurizio Martina, Guido Masera   +3 more
doaj   +1 more source

A 2.0 Gb/s Throughput Decoder for QC-LDPC Convolutional Codes

, 2013
This paper propose a decoder architecture for low-density parity-check convolutional code (LDPCCC). Specifically, the LDPCCC is derived from a quasi-cyclic (QC) LDPC block code.
Chen, Xu, Lau, Francis C. M., Sham, Chiu-Wing, Tam, Wai M., Zhao, Yue   +4 more
core   +1 more source

Encoding of QC-LDPC Codes of Rank Deficient Parity Matrix

Journal of Engineering, 2016
the encoding of long low density parity check (LDPC) codes presents a challenge compared to its decoding. The Quasi Cyclic (QC) LDPC codes offer the advantage for reducing the complexity for both encoding and decoding due to its QC structure.
Mohammed Kasim Mohammed Al-Haddad
doaj   +2 more sources

Analysis of reaction and timing attacks against cryptosystems based on sparse parity-check codes

, 2019
In this paper we study reaction and timing attacks against cryptosystems based on sparse parity-check codes, which encompass low-density parity-check (LDPC) codes and moderate-density parity-check (MDPC) codes.
A Becker, A Nilsson, DJ Bernstein, E Berlekamp, E Eaton, E Prange, H Niederreiter, J Stern, K Kobara, M Baldi, M Baldi, P Santini, PJ Lee, Q Guo, RG Gallager, T Fabšič, T Fabšič   +16 more
core   +1 more source

A High Throughput Implementation of QC-LDPC Codes for 5G NR

IEEE Access, 2019
Quasi-cyclic low-density parity-check (QC-LDPC) codes are the choice for data channels in the fifth generation (5G) new radio (NR). At the transmitter side, code bits from the QC-LDPC encoder are delivered to the rate matcher.
Hao Wu, Huayong Wang
doaj   +1 more source