Results 251 to 260 of about 196,937 (287)
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Quiescent current estimation based on quality requirements
Digest of Papers Eleventh Annual 1993 IEEE VLSI Test Symposium, 2002Presents a novel approach to estimate the I/sub ddq/ current in faulty CMOS integrated circuits. This new methodology is not based on the prior knowledge of the faulty device resistance. Instead of that, the approach proposes the characterization of the quiescent current by evaluating the minimal power-bus current corresponding to an output voltage ...
F.L. Vargas, M. Nicolaidis, B. Hamdi
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A Self‐contained Trimmable Low Quiescent Current Overvoltage Detector
IEEJ Transactions on Electrical and Electronic Engineering, 2022This paper presents a low‐power self‐contained overvoltage detector. Compared with conventional detectors that consist of stacked Zener diodes, the proposed structure can trim the threshold with binary codes to accommodate system‐level changes. The proposed structure enables trimming by adding a decoder, a biasing circuit, and switches in parallel with
Yidong Yuan +5 more
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Calibration Enabled Scalable Current Sensor Module for Quiescent Current Testing
Journal of Electronic Testing, 2012Semiconductor testing is aimed at screening fabrication defects that impact expected functionality. While catastrophic defects result in non working devices, parametric faults result in marginalities and are of increasing concern with deep sub-micron process technologies.
Sachin Dileep Dasnurkar +1 more
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Quiescent current analysis and experimentation of defective CMOS circuits
Journal of Electronic Testing, 1992Physical defects widely encountered in today's CMOS processes (bridges, gate oxide short (gas) and floating gates) are modeled taking into account the topology of the defective circuit and the parameters of the technology. These models are used to simulate at electrical level the behavior of a simple 3-inverter chain with a defective inverter.
Segura, J A +4 more
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Low quiescent current LDO with improved load transient
2008 11th International Biennial Baltic Electronics Conference, 2008Design analysis of CMOS low dropout regulator (LDO)focusing on low quiescent current and load transient improvement methodologies and structures are discussed in this paper.Low quiescent current in battery-operated systems is an intrinsic performance parameter because it partially determines battery life.
S. Strik, V. Strik
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A high current drive cmos output stage with a tunable quiescent current limiting circuit
IEEE Journal of Solid-State Circuits, 2003A CMOS output stage based on a complementary common source with an original quiescent current limiting circuit is presented. The quiescent current can be varied over a wide range by means of a control current with no need to modify the transistor aspect ratios. The output stage has been coupled to a conventional complementary input stage to form a rail-
BRUSCHI, PAOLO +2 more
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Zero quiescent current monostable multivibrator
Radio and Electronic Engineer, 1969A simple monostable multivibrator circuit using a complementary pair of transistors is described. In comparison with the conventional configuration, this circuit has such features that it would need no standing power and a smaller number of components. The commonemitter current amplification factor, hfe, of the transistors may be made as the overriding
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Low quiescent current high speed amplifier for LCD column driver
2007 18th European Conference on Circuit Theory and Design, 2007The design of a very low-current transconductance operational amplifier specifically optimized for a switched-capacitor LCD column driver is presented. Despite its stringent standby current requirements (lower than 700 nA), the amplifier exhibits a DC gain of about 80 dB and, working in class AB, provides a slew rate greater than 20 V/mus under a load ...
S. DI FAZIO +4 more
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Built-in Current Sensor for Quiescent Current Testing in Analog CMOS Circuits
2008 40th Southeastern Symposium on System Theory (SSST), 2008In this paper we present a new built in current sensor (BICS) for quiescent current testing- IDDQ. This sensor has been designed using forward bias technique to limit the supply voltage degradation caused by quiescent current passing through the BICS to 2% of the supply voltage. A CMOS operational amplifier designed for operation at plusmn 2.5 V in 0.5
Siva Yellampalli +2 more
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Reactor circuit with quiescent current compensation
Electrical Engineering, 1954MAGNETIC AMPLIFIERS of the saturable reactor type are used in applications which require a substantially linear relationship between d-c input and d-c output.
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