Results 201 to 210 of about 17,351 (228)

Analysis of a Novel Reseeding Pattern Generator

2021 2nd International Conference on Smart Electronics and Communication (ICOSEC), 2021
Pseudo random sequences are used in testing a logical circuit which can be generated from Linear Feedback Shift Register (LFSR). The proposed pattern generator can work both as an external and internal LFSR depending on the control signal. A number of patterns can be generated by using the proposed design which can be used in logical circuit testing ...
Chinnapapakkagari Sreenivasa Vikranth, Doriginti Mohammad, Geethu Remadevi Somanathan, Ramesh Bhakthavatchalu   +3 more
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Optimized reseeding by seed ordering and encoding

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2005
Mixed-mode logic built-in self-test (BIST) applies both pseudorandom test patterns and deterministic test patterns [from an automatic test pattern generation (ATPG) tool] to the combinational portion of the circuit under test. Each scan-test cycle consists of: 1) shifting a test pattern into the scan chains; 2) capturing the response to that pattern ...
A.A. Al-Yamani, S. Mitra, E.J. McCluskey
openaire   +1 more source

Impact Seeding and Reseeding in the Inner Solar System

Astrobiology, 2005
Assuming that asteroidal and cometary impacts onto Earth can liberate material containing viable microorganisms, we studied the subsequent distribution of the escaping impact ejecta throughout the inner Solar System on time scales of 30,000 years. Our calculations of the delivery rates of this terrestrial material to Mars and Venus, as well as back to ...
Brett, Gladman, Luke, Dones, Harold F, Levison, Joseph A, Burns   +3 more
openaire   +2 more sources

Reseeding LFSR for Test Pattern Generation

2019 International Conference on Communication and Signal Processing (ICCSP), 2019
Testing of circuits became difficult as the scale of integration is increasing as said in Moore’s Law. Conventional testing approach is not sufficient with the growth of device counts and density. Testing helps the developer to investigate faults and error present in developed circuit which helps to reduce time require to test and thus decreases ...
Patare Snehal Dilip, Geethu Remadevi Somanathan, Ramesh Bhakthavatchalu   +2 more
openaire   +1 more source

Two-level compression through selective reseeding

2013 IEEE International Test Conference (ITC), 2013
As scan compression becomes ubiquitous, ever more complex designs require higher compression. This paper presents a novel, two-level compression system for scan input data generated by deterministic test generation. First, load care bits and X-control input data are encoded into PRPG seeds; next, seeds are selectively shared for further compression ...
P. Wohl, J.A. Waicukauski, F. Neuveux, G.A. Maston, N. Achouri, J.E. Colburn   +5 more
openaire   +1 more source

Reseeding Research in the Intermountain Region

Journal of Range Management, 1950
ORGANIZED reseeding research within the Forest Service was begun in the Intermountain region in 1935. Prior to that time, reseeding investigations had been fragmentary and lacked continuity. The scale of research could not cope with the need for restoring the millions of acres of depleted range land.
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Test vector encoding using partial LFSR reseeding

Proceedings International Test Conference 2001 (Cat. No.01CH37260), 2002
A new form of LFSR reseeding that provides higher encoding efficiency and hence greater reduction in test data storage requirements is described. Previous forms of LFSR reseeding have been static (i.e. test generation is stopped and the seed is loaded at one time) and have required full reseeding (i.e. n=r bits are used for an r-bit LFSR). The new form
C.V. Krishna, A. Jas, N.A. Touba
openaire   +1 more source

A New LFSR Reseeding Method for BIST

2006 8th International Conference on Solid-State and Integrated Circuit Technology Proceedings, 2006
This paper presents a new BIST reseeding method that can significantly increase the ratio of test data compression using one LFSR seed to encode multiple deterministic test patterns. Experimental results on ISCAS89 benchmark circuits show that this method has about 30% reduction of the seed ...
Yong-zhi Yan, Hong Wang, Zhi-jia Yang, Song Yang   +3 more
openaire   +1 more source

LFSR-reseeding scheme for achieving test coverage

2013 International Conference on Information Communication and Embedded Systems (ICICES), 2013
As the size and complexity of systems-on-chips continues to grow, the power dissipation during testing becomes very significant problem. During scan shifting, more transitions occur in the flip-flops compared to what occurs during normal functional operation.
M. Kalaiselvi, K. S. Neelukumari
openaire   +1 more source

Efficient LFSR Reseeding Technique

This research introduces a novel approach to optimize LFSR reseeding in logic BIST by utilizing a new test pattern generator with the Seed Initialization Method (SIM). Unlike traditional methods which require additional memory for storing seeds this approach eliminates the need for such storage.
openaire   +1 more source