Results 51 to 60 of about 3,710,915 (96)
Two loop vertices and tree level multicollinear limits in QCD [PDF]
, 2005 We present a summary of the methods required to solve loop-integrals and their reduction to Master Integrals. We then present the expansion in d = 4 - 2e of the Master Integrals required for the two loop massless vertex diagrams with three off-shell legs.
Birthwright, Thomas G. +2 more
core
, 2009 This paper presents a chopper instrumentation amplifier for interfacing precision thermistor bridges. For high CMRR and DC gain, the amplifier employs a three-stage current-feedback topology with nested-Miller compensation. By chopping both the input and
Wu, R. +5 more
core +2 more sources
Lattice-Renormalization of the Polyakov Loop [PDF]
, 2003 Zantow F. Lattice-Renormalization of the Polyakov Loop.
Zantow, Felix
core
After our 2022 seminar with Marc Porée, and our 2023 seminar with Jeremy Elprin on Keats, Loop is proud to present the 2024 agrégation seminar: Claire Vial and Agnès Blandeau: On Sir Gawain and the Green Knight (text and film) Amélie Ducroux : On T.S ...
The LOOP team
core +1 more source
Input current ripple reduction of DC/DC converters
, 2023 The input current ripple problem of DC/DC converters receives more and more attention recently. To meet the increasingly demanding requirements, the fundamental components of the current ripple are researched and the corresponding current ripple ...
Shuai Wang +6 more
core +1 more source
Loop Leaping with Closures [PDF]
, 2012 Loop leaping is the colloquial name given to a form of program analysis in which summaries are derived for nested loops starting from the innermost loop and proceeding in a bottom-up fashion considering one more loop at a time.
Sebastian Biallas +7 more
core +1 more source
Computing ripple effect for software maintenance
, 2001 Recent software maintenance models have included impact analysis and accounting for ripple effect as one of their stages. This paper describes and explains the reformulation of Yau and Collofello's ripple-effect algorithm and its validity within the ...
Black, S.E.
core +1 more source
FPGA Implementation of ADPLL with Ripple Reduction Techniques [PDF]
, 2012 In this paper FPGA implementation of ADPLL using Verilog is presented. ADPLL with ripple reduction techniques is also simulated and implemented on FPGA.
Kusum Lata, Manoj Kumar
core +1 more source
Multi-Channel Neural Recording Implants: A Review. [PDF]
Sensors (Basel), 2020 Hashemi Noshahr F, Nabavi M, Sawan M.
europepmc +1 more source