Results 291 to 300 of about 22,912 (307)
Some of the next articles are maybe not open access.

RISC-V

Qusay F. Hassan, Assim Sagahyroon
openaire   +1 more source

Risc-V Random Test Generator

2021 15th International Conference on Advanced Computing and Applications (ACOMP), 2021
Dai Duong Tran   +3 more
openaire   +1 more source

The RISC-V instruction set

2013 IEEE Hot Chips 25 Symposium (HCS), 2013
Andrew Waterman   +5 more
openaire   +1 more source

An Agile Approach to Building RISC-V Microprocessors

IEEE Micro, 2016
Yunsup Lee, Andrew Waterman, Henry Cook
exaly  

Návrh superskalárního RISC-V procesoru

This thesis deals with designing and implementing a superscalar RISC-V processor microarchitecture focused on environments with constrained resources. For that, the microarchitecture exposes a dual-issue seven-stage pipeline with in-order instruction execution. It is described in SystemVerilog and can be easily simulated on a computer.
openaire   +1 more source

Characterizing a RISC-V SRAM-based FPGA implementation against Single Event Upsets using fault injection

Microelectronics Reliability, 2017
Alexis Ramos, Juan Antonio Maestro
exaly  

Near-Threshold RISC-V Core With DSP Extensions for Scalable IoT Endpoint Devices

IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2017
Michael Gautschi   +2 more
exaly  

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