Results 321 to 330 of about 9,109,748 (351)

Accelerated RISC-V for SIKE

2021 IEEE 28th Symposium on Computer Arithmetic (ARITH), 2021
Software implementations of cryptographic algorithms are slow but highly flexible and relatively easy to implement. On the other hand, hardware implementations are usually faster but provide little flexibility and require a lot of time to implement efficiently.
Mehran Mozaffari-Kermani, Reza Azarderakhsh, Rami Elkhatib   +2 more
openaire   +2 more sources

A Framework for Fault Tolerance in RISC-V

2022 IEEE Intl Conf on Dependable, Autonomic and Secure Computing, Intl Conf on Pervasive Intelligence and Computing, Intl Conf on Cloud and Big Data Computing, Intl Conf on Cyber Science and Technology Congress (DASC/PiCom/CBDCom/CyberSciTech), 2022
Microcontrollers require protection against transient and permanent faults when being utilized for safety-critical and highly reliable applications. Fail safe Dual Core Lockstep architectures are widely used in the automotive domain; the aerospace domain utilizes fail functional TMR or higher redundancy.
Dörflinger, Alexander, Kleinbeck, Benedikt, Albers, Mark, Michalik, Harald, Moya, Martin   +4 more
openaire   +2 more sources

RISC-V Online Tutor

2021
This paper presents the RISC-V Online Tutor course which provides structured, self-paced RISC-V architecture and applications training. The course browser transparently interacts with remote RISC-V hardware, implemented on an FPGA array. The course is implemented and supported by the reported vicilogic platform which provides online learning, remote ...
Laszlo Bako, Fearghal Morgan, Frederic Rousseau, Joseph Clancy, Arthur Beretta, Frank Callaly, Roshan George, Ian Gallivan   +7 more
openaire   +2 more sources

22.1 A 12.4TOPS/W @ 136GOPS AI-IoT System-on-Chip with 16 RISC-V, 2-to-8b Precision-Scalable DNN Acceleration and 30%-Boost Adaptive Body Biasing

IEEE International Solid-State Circuits Conference, 2023
Emerging Artificial Intelligence-enabled Internet-of-Things (Al-loT) SoCs [1–4] for augmented reality, personalized healthcare and nano-robotics need to run a large variety of tasks within a power envelope of a few tens of mW: compute-intensive but bit ...
Francesco Conti, D. Rossi, G. Paulin, Angelo Garofalo, Alfio Di Mauro, Georg Rutishauser, G. Ottavi, M. Eggimann, Hayate Okuhara, V. Huard, O. Montfort, Lionel Jure, Nils Exibard, Pascal Gouedo, M. Louvat, Emmanuel Botte, L. Benini   +16 more
semanticscholar   +1 more source

Performance Evaluation of RISC-V Architecture

2021
This study shows the Gem5 simulator to evaluate the performance of a RISC-V architecture-based processor. The Gem5 simulator is used to investigate the processor architecture's performance metrics such as bandwidth, latency, throughput, branch prediction, pipeline stages, and memory hierarchy.
Hemant Jeeven Magadam, Lakshmaiah Alluri, M. Bhaskar   +2 more
openaire   +3 more sources

The Case for RISC-V in Space

2019
This paper presents preliminary position on the use of the novel, free and open RISC-V Instruction Set Architecture (ISA) for on-board electronics in space. The modular nature of this ISA, the availability of a rich software ecosystem, a rapidly growing community and a pool of open-source IP cores will allow Space Industry to spin-in developments from ...
Stefano Di Mascio, Alessandra Menicucci, Gianluca Furano, Claudio Monteleone &, Marco Ottavi   +4 more
openaire   +2 more sources

Will RISC-V revolutionize computing?

Communications of the ACM, 2020
The open instruction set for microprocessors promises to reshape computing and introduce new, more powerful capabilities.
openaire   +1 more source

A lightweight ISE for ChaCha on RISC-V

2021 IEEE 32nd International Conference on Application-specific Systems, Architectures and Processors (ASAP), 2021
ChaCha is a high-throughput stream cipher designed with the aim of ensuring high-security margins while achieving high performance on software platforms. RISC-V, an emerging, free, and open Instruction Set Architecture (ISA) is being developed with many instruction set extensions (ISE).
Daniel Page, Thinh Hung Pham, Ben Marshall   +2 more
openaire   +2 more sources

X-HEEP: An Open-Source, Configurable and Extendible RISC-V Microcontroller for the Exploration of Ultra-Low-Power Edge Accelerators

arXiv.org
The field of edge computing has witnessed remarkable growth owing to the increasing demand for real-time processing of data in applications. However, challenges persist due to limitations in performance and power consumption. To overcome these challenges,
Simone Machetti, Pasquale Davide Schiavone, Thomas Christoph Müller, Miguel Peón Quirós, David Atienza   +4 more
semanticscholar   +1 more source

A Security RISC: Microarchitectural Attacks on Hardware RISC-V CPUs

IEEE Symposium on Security and Privacy, 2023
Microarchitectural attacks threaten the security of computer systems even in the absence of software vulnerabilities. Such attacks are well explored on x86 and ARM CPUs, with a wide range of proposed but not-yet deployed hardware countermeasures.
Lukas Gerlach, Daniel Weber, Ruiyi Zhang, Michael Schwarz   +3 more
semanticscholar   +1 more source