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IEEE Transactions on Circuits and Systems Part 1: Regular Papers
Digital computing-in-memory (DCIM) that merges computing logic into memory has been proven to be an efficient architecture for accelerating multiply-and-accumulates (MACs).
Wente Yi +7 more
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Digital computing-in-memory (DCIM) that merges computing logic into memory has been proven to be an efficient architecture for accelerating multiply-and-accumulates (MACs).
Wente Yi +7 more
semanticscholar +1 more source
An Eight-Core RISC-V Processor With Compute Near Last Level Cache in Intel 4 CMOS
IEEE Journal of Solid-State Circuits, 2023An eight-core 64-b processor extends RISC-V to perform multiply–accumulate (MAC) within the shared last level cache (LLC). Instead of moving data from the LLC to the core, compute near last level cache (CNC) adds MAC to the LLC datapath and performs ...
Gregory K. Chen +3 more
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MiniFloats on RISC-V Cores: ISA Extensions With Mixed-Precision Short Dot Products
IEEE Transactions on Emerging Topics in ComputingLow-precision floating-point (FP) formats have recently been intensely investigated in the context of machine learning inference and training applications.
Luca Bertaccini +5 more
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HAMSA-DI: A Low-Power Dual-Issue RISC-V Core Targeting Energy-Efficient Embedded Systems
IEEE Transactions on Circuits and Systems Part 1: Regular PapersThe RISC-V architecture has recently emerged as a popular open source option for the design of general purpose cores with a wide spectrum of operating specifications.
Yehuda Kra +3 more
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IEEE Transactions on Circuits and Systems Part 1: Regular Papers
The increasing interest in RISC-V from both academia and industry has motivated the development and release of a number of free, open-source cores based on the RISC-V instruction set architecture.
Jin Park +6 more
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The increasing interest in RISC-V from both academia and industry has motivated the development and release of a number of free, open-source cores based on the RISC-V instruction set architecture.
Jin Park +6 more
semanticscholar +1 more source
Performance characterisation of the 64-core SG2042 RISC-V CPU for HPC
ISC WorkshopsWhilst RISC-V has grown phenomenally quickly in embedded computing, it is yet to gain significant traction in High Performance Computing (HPC). However, as we move further into the exascale era, the flexibility offered by RISC-V has the potential to be ...
Nick Brown, Maurice Jamieson
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Information Flow Tracking in RISC-V [PDF]
2019 IEEE 16th International Conference on Smart Cities: Improving Quality of Life Using ICT & IoT and AI (HONET-ICT), 2019 In the process of globalization, heterogeneous SoCs play an important role in an embedded application, security aspects of such systems are crucial. The system is susceptible to many attacks out of which we focus on the run-time software attacks which causes memory corruption.
Fareena Saqib, Geraldine Shirley
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A RISC-V “V” VP: Unlocking Vector Processing for Evaluation at the System Level
Design, Automation and Test in EuropeIn this paper we introduce the first free- and open-source SystemC TLM based RISC-V Virtual Prototype (VP) with support for the RISC-V “V” Vector Extension (RVV) Version 1.0.
Manfred Schlägl +2 more
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RISC-V Extension for Lightweight Cryptography
2020 23rd Euromicro Conference on Digital System Design (DSD), 2020Lightweight Cryptography (LWC) is suitable for IoTs which require a high level of security while keeping a low complexity. Many lightweight cryptographic algorithms have been proposed to satisfy these requirements. But there is currently no emerging standard concerning the symmetric block ciphering, as every algorithm has its own advantage.
Etienne Tehrani +3 more
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SC24-W: Workshops of the International Conference for High Performance Computing, Networking, Storage and Analysis
In recent years, interest in RISC-V computing architectures has moved from academic to mainstream, especially in the field of High Performance Computing where energy limitations are increasingly a concern.
Patrick Diehl +9 more
semanticscholar +1 more source
In recent years, interest in RISC-V computing architectures has moved from academic to mainstream, especially in the field of High Performance Computing where energy limitations are increasingly a concern.
Patrick Diehl +9 more
semanticscholar +1 more source