Results 341 to 350 of about 9,109,748 (351)

Complete and Efficient Verification for a RISC-V Processor Using Formal Verification

Design, Automation and Test in Europe
Formal verification techniques are computationally complex and the exact time and space complexities are in general not known, which makes the performance of the process unpredictable.
Lennart Weingarten, Kamalika Datta, Abhoy Kole, Rolf Drechsler   +3 more
semanticscholar   +1 more source

A Compiler Comparison in the RISC-V Ecosystem

2020 International Conference on Omni-layer Intelligent Systems (COINS), 2020
The GNU Compiler Collection (GCC) is the traditional compiler for most embedded systems, since it supports many different instruction set architectures (ISA) in its back-end. GCC has also been the first compiler that supported the RISC-V ISA. Since a while Clang/LLVM has gained more and more interest in the embedded software community. Recently, RISC-V
Wolfgang Nebel, Mehrdad Poorhosseini, Kim Grüttner   +2 more
openaire   +2 more sources

Optimizing CNN Computation Using RISC-V Custom Instruction Sets for Edge Platforms

IEEE transactions on computers
Benefit from the custom instruction extension capabilities, RISC-V architecture can be optimized for many domain-specific applications. In this paper, we propose seven RISC-V SIMD (single instruction multiple data) custom instructions that can ...
Shihang Wang, Xingbo Wang, Zhiyuan Xu, Bingzhen Chen, Chenxi Feng, Qi Wang, T. Ye   +6 more
semanticscholar   +1 more source

Accelerating stencils on the Tenstorrent Grayskull RISC-V accelerator

SC24-W: Workshops of the International Conference for High Performance Computing, Networking, Storage and Analysis
The RISC-V Instruction Set Architecture (ISA) has enjoyed phenomenal growth in recent years, however it still to gain popularity in HPC. Whilst adopting RISC-V CPU solutions in HPC might be some way off, RISC-V based PCIe accelerators offer a middle ...
Nick Brown, Ryan Barton
semanticscholar   +1 more source

Enhancing RISC-V Processor Performance in Harsh Environments through Data Cache Optimization

2024 Panhellenic Conference on Electronics & Telecommunications (PACET)
Processor performance is often limited by cache efficiency, a critical aspect in any signal processing task. A RISC-V processor combined with the cache presented in this paper will be part of a deep drilling component manufactured to further automate the
Jan-Luca Frühauf, Malte Hawich, Holger Blume   +2 more
semanticscholar   +1 more source

The Scale4Edge RISC-V Ecosystem

2022 Design, Automation & Test in Europe Conference & Exhibition (DATE), 2022
Ecker, Wolfgang, Adelt, Peer, Müller, Wolfgang, Heckmann, Reinhold, Kristic, Milos, Herdt, Vladimir, Drechsler, Rolf, Angst, Gerhard, Wimmer, Ralf, Mauderer, Andreas, Stahl, Rafael, Emrich, Karsten, Müller-Gritschneder, Daniel, Becker, Bernd, Scholl, Philipp, Jentzsch, Eyck, Schlamelcher, Jan, Grüttner, Kim, Palomero Bernardo, Paul, Bringmann, Oliver, Damian, Mihaela, Oppermann, Julian, Koch, Andreas, Bormann, Jörg, Partzsch, Johannes, Mayr, Christian, Kunz, Wolfgang   +26 more
openaire   +2 more sources

Implementation of PWM Using RISC-V Processor

2024 International Conference on Advances in Modern Age Technologies for Health and Engineering Science (AMATHE)
Implementation of Pulse width modulation(PWM) using RISC-V processor is the main topic of this work. RISC-V is a free and open-source Instruction Set Architecture (ISA) designed for cloud computing, embedded systems, and academic use.
Prem Kanjarbhat, Pooja Chandaragi, Uday V Wali   +2 more
semanticscholar   +1 more source

Procesador RISC-V segmentado

2023
Este proyecto de fin de grado consiste en el diseño e implementación de un procesador basado en la arquitectura libre RISC-V en una FPGA de Amd-Xilinx desde cero, es decir, sin utilizar ninguna clase de bloque IP ni código externo, aplicando la técnica de segmentación para aumentar las prestaciones del mismo.
openaire   +1 more source

Efficient Cryptography on the RISC-V Architecture

2019
RISC-V is a promising free and open-source instruction set architecture. Most of the instruction set has been standardized and several hardware implementations are commercially available. In this paper we highlight features of RISC-V that are interesting for optimizing implementations of cryptographic primitives. We provide the first optimized assembly
openaire   +3 more sources

High-Performance RISC-V Emulation

2020
RISC-V is an open ISA that has been calling the attention worldwide by its fast growth and adoption. It is already supported by GCC, Clang and the Linux Kernel. However, none of the currently available RISC-V emulators are capable of providing good, near-native, emulation performance.
Vanderson Martins do Rosario, Edson Borin, Leandro Lupori   +2 more
openaire   +2 more sources