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A Health Economic Assessment of Relaxation of COVID-19 Control in England 2021
Cooper A, Keeling MJ.
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2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010), 2010
Technology scaling has an increasing impact on the resilience of CMOS circuits. This outcome is the result of (a) increasing sensitivity to various intrinsic and extrinsic noise sources as circuits shrink, and (b) a corresponding increase in parametric variability causing behavior similar to what would be expected with hard (topological) faults.
Sani R. Nassif, Nikil Mehta, Yu Cao 0001
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Technology scaling has an increasing impact on the resilience of CMOS circuits. This outcome is the result of (a) increasing sensitivity to various intrinsic and extrinsic noise sources as circuits shrink, and (b) a corresponding increase in parametric variability causing behavior similar to what would be expected with hard (topological) faults.
Sani R. Nassif, Nikil Mehta, Yu Cao 0001
openaire +1 more source