Results 131 to 140 of about 568 (183)

Safety and efficacy of using a large bore guide catheter through a short 8-Fr sheath for transradial neurointerventional procedures. [PDF]

Interv Neuroradiol
Reddi P, Goldman D, Tabani H, Hashmi A, Mehta A, Kellner CP, De Leacy R, Mocco J, Majidi S.   +8 more
europepmc   +1 more source

Semantic TRIZ feasibility in technology development, innovation, and production: A systematic review. [PDF]

Heliyon
Ghane M, Ang MC, Cavallucci D, Abdul Kadir R, Ng KW, Sorooshian S.   +5 more
europepmc   +1 more source

Angiography-like neurovascular training without radiation utilizing optical cameras and virtual roadmap imaging. [PDF]

Interv Neuroradiol
Klebingat S, Schwab R, Feierabend S, Stolze F, Behme D.   +4 more
europepmc   +1 more source

Mapping the technological evolution of generative AI: a patent network analysis. [PDF]

Sci Rep
Mohammadi N, Heidary Dahooie J, Bengari AA, Rahimi A.   +3 more
europepmc   +1 more source

Clinical use of reserved guide wire fenestration and Viabahn-covered stent in Stanford type B aortic dissection with left subclavian artery involvement. [PDF]

J Int Med Res
Zhu H, Zhu H.
europepmc   +1 more source

Developing global research roadmaps for alternatives to antimicrobials in animal health: a participatory expert-driven approach

MARIANO V, Newman M, Messori S, Morrow A.   +3 more
europepmc   +1 more source

Roadmapping Roadmapping: Strategic planning for roadmapping systems

Frontiers of Engineering Management
AbstractRoadmapping is a well-established technique in the context of innovation and strategy, with the potential to support organizations address the complex transformative challenges facing humanity in the 21st century. This is enabled by its systems-based architecture and visual form of roadmaps, supporting communication and reduction of information
Robert Phaal, Phaal Robert
exaly   +4 more sources

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A resilience roadmap

2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010), 2010
Technology scaling has an increasing impact on the resilience of CMOS circuits. This outcome is the result of (a) increasing sensitivity to various intrinsic and extrinsic noise sources as circuits shrink, and (b) a corresponding increase in parametric variability causing behavior similar to what would be expected with hard (topological) faults.
Sani R. Nassif, Nikil Mehta, Yu Cao 0001
openaire   +1 more source