Results 1 to 10 of about 42,050 (93)
Optimization of Branch Pipe Routing Considering Tee Constraint Ant Lion
IEEE Access, 2023 Considering the complex nature of branch pipes, which typically exhibit one-to-many characteristics, a transformation is implemented to facilitate one-to-one pipe routing.
Haicheng Shen, Shiyu Liu
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Interactive Visualization of the Printed Circuits Tracing Algorithms for Educational Purposes
Цифровая трансформация, 2023 A software module that allows interactive demonstration of maze routing algorithms for tracing printed conductors, which, during their operation, use a grid representation of a discrete working space of a printed circuit board has been developed.
D. O. Petrov
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IEEE Access, 2022 Continued scaling in accordance with Moore’s law is becoming increasingly difficult. Pitch shrinkage and standard cell height reduction via design technology co-optimization with design rules have sustained this scaling until recently. However, we
Chung-Kuan Cheng +3 more
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VLSI Circuit Optimization for 8051 MCU
International Journal of Technology, 2018 With the aid of Electronic Design Automation tools, we perform circuit optimization on the 8051 microcontroller. The original 8051 microcontroller operates at a clock frequency 12 MHz, and it was designed based on 3.5-µm process technology.
Kim Ho Yeap +4 more
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Fog computing, applications , security and challenges, review [PDF]
, 2018 The internet of things originates a world where on daily basis objects can join the internet and interchange information and in addition process, store, gather them from the nearby environment, and effectively mediate on it.
Chai, Chuah Wen, Rahman, Gohar
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Boolean Satisfiability in Electronic Design Automation [PDF]
, 2000 Boolean Satisfiability (SAT) is often used as the underlying model for a significant and increasing number of applications in Electronic Design Automation (EDA) as well as in many other fields of Computer Science and Engineering. In recent years, new and
Marques-Silva, J. P., Sakallah, K. A.
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Adoption of vehicular ad hoc networking protocols by networked robots [PDF]
, 2012 This paper focuses on the utilization of wireless networking in the robotics domain. Many researchers have already equipped their robots with wireless communication capabilities, stimulated by the observation that multi-robot systems tend to have several
Demeester, Piet +2 more
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Cycle-accurate evaluation of reconfigurable photonic networks-on-chip [PDF]
, 2010 There is little doubt that the most important limiting factors of the performance of next-generation Chip Multiprocessors (CMPs) will be the power efficiency and the available communication speed between cores.
Artundo, Iñigo +4 more
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A High-level EDA Environment for the Automatic Insertion of HD-BIST Structures [PDF]
, 2000 This paper presents a High-Level EDA environment based on the Hierarchical Distributed BIST (HD-BIST), a flexible and reusable approach to solve BIST scheduling issues in System-on-Chip applications.
Benso, Alfredo +4 more
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On the suitability and development of layout templates for analog layout reuse and layout-aware synthesis [PDF]
, 2005 Accelerating the synthesis of increasingly complex analog integrated circuits is key to bridge the widening gap between what we can integrate and what we can design while meeting ever-tightening time-to-market constraints.
Castro López, Rafael +2 more
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