Results 1 to 10 of about 1,782 (230)

Optimization of Branch Pipe Routing Considering Tee Constraint Ant Lion

IEEE Access, 2023
Considering the complex nature of branch pipes, which typically exhibit one-to-many characteristics, a transformation is implemented to facilitate one-to-one pipe routing.
Haicheng Shen, Shiyu Liu
doaj   +1 more source

Interactive Visualization of the Printed Circuits Tracing Algorithms for Educational Purposes

Цифровая трансформация, 2023
A software module that allows interactive demonstration of maze routing algorithms for tracing printed conductors, which, during their operation, use a grid representation of a discrete working space of a printed circuit board has been developed.
D. O. Petrov
doaj   +1 more source

Monolithic 3D Semiconductor Footprint Scaling Exploration Based on VFET Standard Cell Layout Methodology, Design Flow, and EDA Platform

IEEE Access, 2022
Continued scaling in accordance with Moore’s law is becoming increasingly difficult. Pitch shrinkage and standard cell height reduction via design technology co-optimization with design rules have sustained this scaling until recently. However, we
Chung-Kuan Cheng, Chia-Tung Ho, Daeyeal Lee, Bill Lin   +3 more
doaj   +1 more source

VLSI Circuit Optimization for 8051 MCU

International Journal of Technology, 2018
With the aid of Electronic Design Automation tools, we perform circuit optimization on the 8051 microcontroller. The original 8051 microcontroller operates at a clock frequency 12 MHz, and it was designed based on 3.5-µm process technology.
Kim Ho Yeap, Kang Wei Thee, Koon Chun Lai, Humaira Nisar, K. Chandrasekaran Krishnan   +4 more
doaj   +1 more source

Hierarchical Deep Reinforcement Learning for Multi-Objective Integrated Circuit Physical Layout Optimization With Congestion-Aware Reward Shaping

IEEE Access
Physical layout optimization in integrated circuit (IC) design remains a critical challenge as semiconductor technology scales toward advanced nodes, where traditional electronic design automation (EDA) tools struggle to simultaneously optimize multiple ...
Haijian Zhang, Yao Ge, Xiuyuan Zhao, Jiyuan Wang   +3 more
doaj   +1 more source

A generation method for PCB routing based on generative adversarial networks

Dianzi Jishu Yingyong
To address the increasingly high time cost of traditional automatic routing algorithms in the design process of printed circuit boards (PCB), a routing generation method based on generative adversarial networks is proposed. This method transforms the PCB
Zhu Peiran, ZHU Kaiben, Liu Wei
doaj   +1 more source

METHODOLOGY AND BACKEND FLOW OPTIMIZATION FOR 3D

Journal of Engineering Science (Chişinău)
The article deals with the complexity of the workflow used when integrated circuits are implemented using 2D electronic design automation (EDA) tools and adapting the workflow for 3D integrated circuits.
PLETEA, Ionica-Marcela
doaj   +1 more source

Electronic Computer-Aided Design for Low-Level Modeling of Networks-on-Chip

IEEE Access
This article proposes a Network-on-Chip (NoC) communication subsystem model on the basis of which the Electronic Computer-Aided Design (ECAD) architecture in the form of software is implemented.
Evgeny V. Lezhnev, Vladimir V. Zunin, Aleksandr A. Amerikanov, Aleksandr Y. Romanov   +3 more
doaj   +1 more source

Silicluster v2: A Scalable Open-Source Multi-Project SoC Architecture in Sky130 CMOS Enabling High-Density Modular Integration

IEEE Access
The increasing availability of open-source electronic design automation (EDA) tools and publicly accessible process design kits (PDKs) has expanded access to integrated circuit (IC) development; however, scalable system-level integration frameworks ...
Uriel Jaramillo-Toral, Susana Ortega-Cisneros, Hector Emmanuel Munoz-Zapata, Iraam Antonio Lopez-Salas   +3 more
doaj   +1 more source

Fully automated processor chip design: motivation, challenges and future directions. [PDF]

Natl Sci Rev
Zhang R, Guo J, Cheng S, Chen Y.
europepmc   +1 more source