Results 221 to 230 of about 582,151 (290)

An 8-to-12-Bit Resolution-Reconfigurable SAR ADC With Fast-Window-Switching Technique

IEEE Transactions on Circuits and Systems - II - Express Briefs
This brief presents a resolution-reconfigurable successive-approximation-register (SAR) analog-to-digital converter (ADC). The reconfigurable capacitor digital-to-analog converter (CDAC) is designed to support 8/10/12-bit resolution modes.
Yuhua Liang, Shida Song, Zhangming Zhu
semanticscholar   +1 more source

A 90-dB-SNDR Calibration-Free Fully Passive Noise-Shaping SAR ADC With 4× Passive Gain and Second-Order DAC Mismatch Error Shaping

IEEE Journal of Solid-State Circuits, 2021
Noise-shaping (NS) successive approximation register (SAR) analog-to-digital converters (ADCs) using passive loop filters have drawn the increasing attentions owing to their simplicity, low power, zero static current, and PVT robustness.
Jiaxin Liu, Xing Wang, Zijie Gao, Mingtao Zhan, Xiyuan Tang, Chen-Kai Hsu, Nan Sun   +6 more
semanticscholar   +1 more source

A Mode-Reconfigurable Second-Order NS-SAR ADC With NTF Synchronous Optimization

IEEE Transactions on Circuits and Systems Part 1: Regular Papers
This paper presents a mode-reconfigurable 2nd-order noise-shaping successive-approximation-register (NS-SAR) analog-to-digital converter (ADC) featured with the ability of optimizing the noise transfer function (NTF) synchronously. Three operation modes,
Yuhua Liang, Shida Song, Nuo Xu, Yuke Shen, Zhangming Zhu   +4 more
semanticscholar   +1 more source

A 112-Gb/s PAM-4 Long-Reach Wireline Transceiver Using a 36-Way Time-Interleaved SAR ADC and Inverter-Based RX Analog Front-End in 7-nm FinFET

IEEE Journal of Solid-State Circuits, 2021
A 36-way time-interleaved 56-GS/s 7-bit ADC is designed to realize 112-Gb/s pulse-amplitude modulation (PAM-4) transceiver in a 7-nm FinFET CMOS. The receiver analog front-end stages and the ADC track-and-hold (T/H) buffers are implemented using inverter-
J. Im, Kevin Zheng, Chuen-huei Adam Chou, Lei Zhou, Jae Wook Kim, Stanley Chen, Yundi Wang, Hao-Wei Hung, Kee Hian Tan, Winson Lin, A. Roldan, D. Carey, Ilias Chlis, R. Casey, Ade Bekele, Ying Cao, David Mahashin, H. Ahn, Hongtao Zhang, Y. Frans, Ken Chang   +20 more
semanticscholar   +1 more source

Predictive Noise Shaping SAR ADC

2019 IEEE International Symposium on Circuits and Systems (ISCAS), 2019
In this paper, a novel predictive first-order noise shaping SAR ADC is proposed. Noise-shaping (NS) SAR ADCs have recently gained much attention due to their low power requirements and wide dynamic range. However, for any oversampled ADC, there is a range that each sample will be within guaranteed by input bandwidth.
Jyotindra R. Shakya, Ajmal K. Vadakkan, Gabor C. Temes   +2 more
openaire   +1 more source

A 12-bit 1.5-GS/s Single-Channel Pipelined SAR ADC With a Pipelined Residue Amplification Stage

IEEE Journal of Solid-State Circuits
This article presents a 12-bit 1.5-GS/s single-channel pipelined successive approximation register (SAR) analog-to-digital converter (ADC). The ADC leverages a pipelined residue amplification (RA) stage scheme, early quantization technique, and fast ...
Yingjie Shen, Shubin Liu, Yue Cao, Haolin Han, Hongzhi Liang, Zhicheng Dong, Dengquan Li, R. Ding, Zhangming Zhu   +8 more
semanticscholar   +1 more source

A semi-synchronous SAR ADC

Analog Integrated Circuits and Signal Processing, 2011
A semi-synchronous clocking scheme is proposed for successive approximation register (SAR) analog-to-digital converters (ADCs). The conversion time is dynamically allocated to the comparator decision and to the DAC settling in every bit cycle. This significantly improves the conversion speed.
Tao Tong, Pavan K. Hanumolu, Gabor C. Temes   +2 more
openaire   +1 more source

A 94.3-dB SNDR 184-dB FoMs 4th-Order Noise-Shaping SAR ADC With Dynamic-Amplifier-Assisted Cascaded Integrator

IEEE Solid-State Circuits Letters
This letter presents a fully dynamic 4th-order noise-shaping (NS) successive approximation register (SAR) analog-to-digital converter (ADC) with the proposed 4th-order cascaded integrator using dynamic-amplifier-assisted and passive integration. This ADC
Kai-Cheng Cheng, Soon-Jyh Chang, Chung-Chieh Chen, Shuo-Hong Hung   +3 more
semanticscholar   +1 more source

A 71.5-dB SNDR 475-MS/s Ringamp-Based Pipelined SAR ADC with On-Chip Bit-Weight Calibration

2024 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)
This paper presents a 13-bit 475-MS/s single-channel pipelined SAR ADC, which utilizes a ring amplifier (ringamp) for residue amplification through an improved bias scheme and common-mode feedback (CMFB).
Chao Chen, Zhu Yuan, Peng Cao, Jiawei Xu, Zhiliang Hong   +4 more
semanticscholar   +1 more source

A 100kHz-Bandwidth 98.3dB-SNDR Noise-Shaping SAR ADC with Improved Mismatch Error Shaping and Speed-Up Techniques

2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), 2022
Noise-Shaping (NS) SAR ADCs can have high Dynamic Range (DR) and be easily adopted to IoT, audio and many other applications. This paper proposes four techniques to improve the DR and conversion speed of NS SAR ADCs.
Kazunori Hasebe, Shinichirou Etou, D. Miyazaki, Taiki Iguchi, Yuki Yagishita, Mika Takasaki, Takeru Nogamida, Hiroyuki Watanabe, T. Matsumoto, Yasushi Katayama   +9 more
semanticscholar   +1 more source