Results 231 to 240 of about 582,151 (290)

9.7 A 94.3dB SNDR 184dB FoMs 4th-Order Noise-Shaping SAR ADC with Dynamic-Amplifier-Assisted Cascaded Integrator

IEEE International Solid-State Circuits Conference
The noise-shaping (NS) SAR ADC, which features the advantages of sigma-delta ADCs and SAR ADCs, is high accuracy and low power, so it stands out as a great choice for audio applications of IoT devices.
Kai-Cheng Cheng, Soon-Jyh Chang, Chung-Chieh Chen, Shuo-Hong Hung   +3 more
semanticscholar   +1 more source

SAR ADC algorithm with redundancy

APCCAS 2008 - 2008 IEEE Asia Pacific Conference on Circuits and Systems, 2008
This paper describes a redundant algorithm for a highly reliable Successive Approximation Register (SAR) ADC where mistakes of comparator decision can be digitally-corrected. We generalize a conventional non-binary search algorithm which requires more conversion steps in the SAR ADC than the binary search algorithm, and clarify which decision errors ...
Tomohiko Ogawa, Haruo Kobayashi, Masao Hotta, Yosuke Takahashi, null Hao San, null Nobukazu Takai   +5 more
openaire   +1 more source

9.1 A 2mW 70.7dB SNDR 200MS/s Pipelined-SAR ADC with Continuous-Time SAR-Assisted Detect-and-Skip and Open-then-Close Correlated Level Shifting

IEEE International Solid-State Circuits Conference
The pipelined-SAR ADC has become popular in wide-bandwidth and high-resolution applications due to its power-efficient architecture [1]. In the pursuit of higher ADC speeds while maintaining precision and power efficiency, not only does the conversion ...
Siyuan Ye, Linxiao Shen, Jihang Gao, Jie Li, Zhuoyi Chen, Xinhang Xu, Jiajia Cui, Hao Zhang, Xing Zhang, Le Ye, Ru Huang   +10 more
semanticscholar   +1 more source

A 0.6-V 94-nW 10-Bit 200-kS/s Single-Ended SAR ADC for Implantable Biosensor Applications

IEEE Sensors Journal, 2022
This work presents an ultralow-power 10-bit 200-kS/s single-ended successive approximation register (SAR) analog-to-digital converter (ADC) for implantable biosensor applications.
Xin Zhao, Dengquan Li, Xianghui Zhang, Shubin Liu, Zhangming Zhu   +4 more
semanticscholar   +1 more source

Artificial Neural Network Based Calibration for a 12 b 250 MS/s Pipelined-SAR ADC With Ring Amplifier in 40-nm CMOS

IEEE Transactions on Circuits and Systems Part 1: Regular Papers
This paper presents a 2-stage pipelined-SAR ADC with artificial-neural-network (ANN) based digital calibration algorithm to calibrate the mismatch error in the $1^{\mathrm {st}}$ -stage capacitive DAC (CDAC) and the inter-stage gain error (IGE) together.
Bin Liu, Nannan Li, Xuhui Chen, Zhichao Dai, Yufeng Ge, Zheng Jiang, Huanhuan Qi, Jie Zhang, Jinfu Wang, Xiaofei Wang, Zhenhai Chen, Yan Xue, Hong Zhang   +12 more
semanticscholar   +1 more source

A 2.08-mW 64.4-dB SNDR 400-MS/s Pipelined- SAR ADC Using Mismatch and PVT Variation Tolerant Dynamically Biased Ring Amplifier in 8 nm

IEEE Journal of Solid-State Circuits
In this article, we introduce a new dynamically biased ring amplifier that is tolerant to mismatch and PVT variation without requiring bias calibration, and we verify it in a 12-bit 400-MS/s pipelined-SAR analog-to-digital converter (ADC), fabricated in ...
Yong Lim, Jaehoon Lee, Jongmi Lee, Kwangmin Lim, Seunghyun Oh, Jongwoo Lee   +5 more
semanticscholar   +1 more source

A 13.5-ENOB, 107-μW Noise-Shaping SAR ADC With PVT-Robust Closed-Loop Dynamic Amplifier

IEEE Journal of Solid-State Circuits, 2020
This article presents a second-order noise-shaping (NS) successive approximation register (SAR) analog-to-digital converter (ADC) with a process, voltage, and temperature (PVT)-robust closed-loop dynamic amplifier.
Xiyuan Tang, Xiangxing Yang, Wenda Zhao, Chen-Kai Hsu, Jiaxin Liu, Linxiao Shen, Abhishek Mukherjee, Wei Shi, Shaolan Li, D. Pan, Nan Sun   +10 more
semanticscholar   +1 more source

A 13-Bit ENOB Third-Order Noise-Shaping SAR ADC Employing Hybrid Error Control Structure and LMS-Based Foreground Digital Calibration

IEEE Journal of Solid-State Circuits, 2022
This article presents a third-order noise-shaping (NS) successive approximation register (SAR) analog-to-digital converter (ADC), which exploits a hybrid error control topology to increase the order of the noise-transfer function (NTF).
Qihui Zhang, N. Ning, Zhong Zhang, Jing Li, Kejun Wu, Yong Chen, Qi Yu   +6 more
semanticscholar   +1 more source

Noise-Shaping SAR ADCs

2019
The noise-shaping successive approximation register (NS-SAR) ADC is an emerging hybrid architecture that achieves high resolution and power efficiency simultaneously by combining the merits of the SAR ADC and the Δ Σ ADC. They have the merits of simple, highly digital, and low-voltage tolerant, making them attractive candidates for emerging sensing and
Shaolan Li, Jiaxin Liu, Wenjuan Guo, Nan Sun   +3 more
openaire   +1 more source

A 0.97mW 260MS/s 12b Pipelined-SAR ADC with Ring-TDC-Based Fine Quantizer for PVT Robust Automatic Cross-Domain Scale Alignment

IEEE International Solid-State Circuits Conference, 2022
The pipelined SAR ADC is a promising architecture to achieve high sample rate with high resolution. Residue amplifiers are normally required between pipelined stages to provide sufficient gain for relaxing the noise requirement in subsequent stages ...
Haoyi Zhao, F. Dai
semanticscholar   +1 more source