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Fa-SAT: Fault-aided SAT-based Attack on Compound Logic Locking Techniques

2021 Design, Automation & Test in Europe Conference & Exhibition (DATE), 2021
Logic locking has received significant traction as a one-stop solution to thwart attacks at an untrusted foundry, test facility, and end-user. Compound locking schemes were proposed that integrate a low corruption and a high corruption locking technique to circumvent both tailored SAT-based and structural-analysis-based attacks.
Nimisha Limaye   +2 more
openaire   +3 more sources

Increased Output Corruption and Structural Attack Resilience for SAT Attack Secure Logic Locking

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2021
Current out-of-cone logic locking methodologies provide resilience against the satisfiability (SAT) attack with minimal corruption of the outputs when comparing an activated and locked integrated circuit (IC). In addition, the structure of the modifications to the original logic leaks functional information of the circuit, which allows an adversary to ...
Kyle Juretus, Ioannis Savidis
openaire   +3 more sources

The SAT Attack on IC Camouflaging: Impact and Potential Countermeasures

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2020
Integrated circuit (IC) camouflaging is a promising defense against so-called IC extraction attacks that seek to reverse engineer the netlist of a packaged IC using delayering and imaging techniques. Camouflaging works by hiding the Boolean functionality of selected gates in the netlist from reverse engineering, albeit at the cost of increased gate ...
Mohamed El Massad   +2 more
openaire   +3 more sources

SMARTLock: SAT Attack and Removal Attack-Resistant Tree-Based Logic Locking

IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, 2020
Yung-Chih Chen
openaire   +3 more sources

Modeling SAT-Attack Search Complexity

2020 IEEE International Symposium on Circuits and Systems (ISCAS), 2020
In this paper, a metric based on mathematical modeling is proposed to evaluate the strength in security of a logic-locked circuit against a satisfiability (SAT) based attack. Current approaches estimate the SAT resilience experimentally based on time-to-solve or the number of calls to a SAT-solver.
Saran Phatharodom   +2 more
openaire   +1 more source

SAT-attack Resilience Measure for Access Restricted Circuits

Proceedings of the 2021 Great Lakes Symposium on VLSI, 2021
With the recent introduction of techniques to restrict scan chain access, a new class of deobfuscation problems emerge, in which the threat model, although similar to deobfuscation of a logic locked circuit, forms a novel class of attack. In this paper, the concept of a logic restricted circuit is generalized and defined.
Saran Phatharodom   +2 more
openaire   +1 more source

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