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Lightweight Implementations of SHA-3 Candidates on FPGAs
2011The NIST competition for developing the new cryptographic hash algorithm SHA-3 has entered its third round. One evaluation criterion is the ability of the candidate algorithm to be implemented on resource-constrained platforms. This includes FPGAs for embedded and hand-held devices.
Jens-Peter Kaps +6 more
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On the hardware implementation efficiency of SHA-3 candidates
2010 17th IEEE International Conference on Electronics, Circuits and Systems, 2010The most well known and officially used hash function is the Secure Hash Algorithm-1 (SHA-1) and Secure Hash Algorithm-2 (SHA-2). In recent years serious attacks have been published against SHA-1. This led the National Institute of Standard and Technology (NIST) to organize an effort to develop a modern and more secure hash algorithms through a hash ...
Paris Kitsos, Nicolas Sklavos 0001
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Integral Distinguishers of Some SHA-3 Candidates
2010In this paper, we study structural Integral properties on reduced versions of the compression functions of some SHA-3 candidates: Hamsi-256, LANE-256 and Grostl-512. More precisely, we improve on the Integral distinguishers of Hamsi-256 (less time complexity or deterministic instead of probabilistic) and present the first known Integral distinguishers ...
Marine Minier +2 more
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Extracts from the SHA-3 Competition
2013The story of the SHA-3 competition starts with the presentation of surprisingly efficient attacks on several modern hash functions at Eurocrypt 2005 [1, 2] and at Crypto 2005 [3, 4]. Collisions were given for the hash functions MD4, MD5, RIPEMD and SHA-0.
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Pipelined SHA-3 Implementations on FPGA
Proceedings of the Second Workshop on Cryptography and Security in Computing Systems, 2015Efficient and high-throughput designs of hash functions will be in great demand in the next few years, given that every IPv6 data packet is expected to be handled with some kind of security features.In this paper, pipelined implementations of the new SHA-3 hash standard on FPGAs are presented and compared aiming to map the design space and the choice ...
Harris E. Michail +2 more
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High Throughput Pipelined Implementation of the SHA-3 Cryptoprocessor
2020 32nd International Conference on Microelectronics (ICM), 2020Today, in the modern world of digital communications, sensitive information is transmitted via public networks. It is essential to ensure the privacy of their transmission with confidentiality, security and integrity using techniques like hashing. An optimized and high throughput implementation of Secure Hash Algorithm-3 (SHA-3) in hardware is a vital ...
Argyrios Sideris +2 more
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2020
If X is sender of a message and Y is the receiver of the same, then X encrypts the same with Y’s public key and then sends the encrypted data to Y. It confirms about authenticity and authorization of receiver. If X sends message and Y receives, X encrypts the message with X’s private key and sends the encrypted data to Y.
Sandip Ghoshal +3 more
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If X is sender of a message and Y is the receiver of the same, then X encrypts the same with Y’s public key and then sends the encrypted data to Y. It confirms about authenticity and authorization of receiver. If X sends message and Y receives, X encrypts the message with X’s private key and sends the encrypted data to Y.
Sandip Ghoshal +3 more
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On the implementation of mceliece with CCA2 indeterminacy by SHA-3
2014 IEEE International Symposium on Circuits and Systems (ISCAS), 2014This paper deals with the design and implementation of the post-quantum public-key algorithm McEliece. Seamless incorporation of a new error generator and new SHA-3 module provides higher indeterminacy and more randomization of the original McEliece algorithm and achieves CCA2 security standard.
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FPGA Implementations of the Round Two SHA-3 Candidates
2010 International Conference on Field Programmable Logic and Applications, 2010The second round of the NIST-run public competition is underway to find a new hash algorithm(s) for inclusion in the NIST Secure Hash Standard (SHA-3). This paper presents the full implementations of all of the second round candidates in hardware with all of their variants.
Brian Baldwin +6 more
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SHA-3-LPHP: Hardware Acceleration of SHA-3 for Low-Power High-Performance Systems
2021 IEEE International Symposium on Software Reliability Engineering Workshops (ISSREW), 2021Yuta Akiya +6 more
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