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Test Generation for Short-Circuit Faults in Digital Circuits
2014In the first part, the paper presents a test calculation principle which serves for producing tests of logic faults in digital circuits. The name of the principle is composite justification. The considered fault model includes stuck-at-0/1 logic faults. Both single and multiple faults are included.
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Fault Analysis of DCSST MV Side Bipolar Short Circuit
2023 IEEE International Conference on Advanced Power System Automation and Protection (APAP), 2023Kaixin Zhang, Shenxing Shi, Xinzhou Dong
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Open-Circuit IGBT Fault Detection and Location Isolation for Cascaded Multilevel Converters
IEEE Transactions on Industrial Electronics, 2017Jacob Lamb, Behrooz Mirafzal
exaly
A Pole-to-Pole Short-Circuit Fault Current Calculation Method for DC Grids
IEEE Transactions on Power Systems, 2017Chengyu Li, Jianzhong Xu, Ting An
exaly
IEEE Transactions on Transportation Electrification, 2018
Kuntal Satpathi, Abhisek Ukil, Josep Pou
exaly
Kuntal Satpathi, Abhisek Ukil, Josep Pou
exaly
In-Situ FPGA Fault Injection with Short-Circuits
2024 IEEE Physical Assurance and Inspection of Electronics (PAINE)Garren Dutto +2 more
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Short-Circuit Fault Protection Strategy for High-Power Three-Phase Three-Wire Inverter
IEEE Transactions on Industrial Informatics, 2012Xuejun Pei, Yong Kang
exaly

