Results 321 to 330 of about 2,460,463 (402)

High-performance lithium battery anodes using silicon nanowires

Nature Nanotechnology, 2008
Candace K Chan, Hailin Peng, Gao Liu
exaly   +2 more sources

Silicon heterojunction solar cell with interdigitated back contacts for a photoconversion efficiency over 26%

Nature Energy, 2017
Serhiy Cherevko
exaly   +2 more sources

Graphene and two-dimensional materials for silicon technology

Nature, 2019
Cedric Huyghebaert, Ching-hua Wang, Deji Akinwande   +2 more
exaly   +2 more sources

Interface passivation for 31.25%-efficient perovskite/silicon tandem solar cells

Science, 2023
Silicon solar cells are approaching their theoretical efficiency limit of 29%. This limitation can be exceeded with advanced device architectures, where two or more solar cells are stacked to improve the harvesting of solar energy.
X. Chin, Deniz Turkay, J. Steele, Saba Tabean, S. Eswara, M. Mensi, Peter Fiala, Christian M. Wolff, Adriana Paracchino, Kerem Artuk, Daniel A. Jacobs, Quentin Guesnay, Florent Sahli, Gaëlle A. L. Andreatta, M. Boccard, Q. Jeangros, C. Ballif   +16 more
semanticscholar   +1 more source

Gluing silicon with silicone

Nuclear Instruments and Methods in Physics Research Section A: Accelerators, Spectrometers, Detectors and Associated Equipment, 1998
Abstract Problems and solutions concerning the gluing of silicon detectors are discussed. The R & D work for the HERA- B vertex detector system led to gluing studies with epoxy and silicone-based adhesives used on ceramics and carbon fibre. The HERA- B solution using a silicone glue is presented.
Abt, I., Fox, H., Moshous, B., Richter, Rainer Helmut, Riechmann, K., Rietz, M., Riedl, J., St. Denis, Richard Dante, Wagner, W.   +8 more
openaire   +3 more sources

Regional Advantage: Culture and Competition in Silicon Valley and Route 128

, 1994
Compares the organization of regional economies, focusing on Silicon Valley's thriving regional network-based system and Route 128's declining independent firm-based system.
A. Chandler, A. Saxenian
semanticscholar   +1 more source

Strained-Silicon on Silicon and Strained-Silicon on Silicon-Germanium on Silicon by Relaxed Buffer Bonding

Journal of The Electrochemical Society, 2006
We report the creation of two novel complementary metal oxide semiconductor CMOS -compatible platforms: strained-silicon onsilicon SSOS and strained-silicon on silicon-germanium on silicon SGOS . SSOS substrate has an epitaxially defined, strained-silicon layer directly on silicon wafer without an intermediate SiGe or oxide layer. SSOS is a homochemical
David M. Isaacson, Thomas A. Langdo, Eugene A. Fitzgerald, Arthur J. Pitera, Gianni Taraschi, Nava Ariel   +5 more
openaire   +2 more sources

Efficient tandem solar cells with solution-processed perovskite on textured crystalline silicon

Science, 2020
Growing perovskite on textured silicon Wide–band gap perovskites could boost the efficiency of silicon solar cells by forming tandem cells, but usually the perovskite must be grown on a smoothed side of the silicon cell because the material grown on the ...
Yi Hou, Erkan Aydin, Michele De Bastiani, C. Xiao, Furkan H. Isikgor, D. Xue, Bin Chen, Hao Chen, B. Bahrami, A. H. Chowdhury, Andrew K. Johnston, S. Baek, Ziru Huang, Mingyang Wei, Yitong Dong, J. Troughton, Rawan Jalmood, Alessandro J. Mirabelli, Thomas G. Allen, E. van Kerschaver, M. Saidaminov, Derya Baran, Q. Qiao, K. Zhu, Stefaan De Wolf, E. Sargent   +25 more
semanticscholar   +1 more source

Computer simulation of local order in condensed phases of silicon.

Physical Review B (Condensed Matter), 1985
A model potential-energy function comprising both two- and three-atom contributions is proposed to describe interactions in solid and liquid forms of Si.
F. Stillinger, T. Weber
semanticscholar   +1 more source

Silicon-On-Silicon Packaging

IEEE Transactions on Components, Hybrids, and Manufacturing Technology, 1984
Honeywell's new packaging technique uses silicon as a multichip substrate. Multiple integrated circuit (IC) chips are flip bonded by controlled collapse joining to a silicon substrate. The silicon substratc provides the interconnections between chips and the next level of interface.
W. Nunne, R. Spielberger, D. Fett, A. Mones, F. Hampton, C. Huang   +5 more
openaire   +2 more sources