Results 311 to 320 of about 315,481 (343)
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Analysis of single-event upsets in a Microsemi ProAsic3E FPGA

2017 18th IEEE Latin American Test Symposium (LATS), 2017
The desirable use of Field-Programmable Gate Arrays (FPGAs) in aerospace & defense field has become a general consensus among IC and embedded system designers. Radiation-hardened (rad-hard) electronics used in this domain is regulated under severe and complex political and commercial treaties.
Paulo Ricardo Cechelero Villa   +10 more
openaire   +1 more source

On-line characterization and reconfiguration for single event upset variations

2009 15th IEEE International On-Line Testing Symposium, 2009
The amount of physical variation among electronic components on a die is increasing rapidly. There is a need for a better understanding of variations in transient fault susceptibility, and for methods of on-line adaptation to such variations. We address three key research questions in this area.
Kenneth M. Zick, John P. Hayes
openaire   +1 more source

Single event upset at ground level

IEEE Transactions on Nuclear Science, 1996
Ground level upsets have been observed in computer systems containing large amounts of random access memory (RAM). Atmospheric neutrons are most likely the major cause of the upsets based on measured data using the Weapons Neutron Research (WNR) neutron beam.
openaire   +1 more source

Observation of single event upsets in analog microcircuits

IEEE Transactions on Nuclear Science, 1993
Selected analog devices were tested for heavy-ion-induced single event upset (SEU). The results of these tests are presented, likely upset mechanisms are discussed, and standards for the characterization of analog upsets are suggested. The OP-15 operational amplifier, which was found to be susceptible to SEU in the laboratory, has also experienced ...
R. Koga   +7 more
openaire   +1 more source

Single Event Upset Error Rates

1997
This chapter together with Chapter 8 provides the major share of the discussion on the practical aspects of single event upset (SEU). This includes formulas for computing SEU in various particle environments. Section 5.2 discusses SEU calculations for heavy-ion cosmic rays at geosynchronous altitudes and Section 5.3 for Van Allen belt protons.
George C. Messenger, Milton S. Ash
openaire   +1 more source

Investigation for Single-Event Upset in MSI Devices

IEEE Transactions on Nuclear Science, 1981
This paper describes the results of the first known test for cosmic-ray effects exclusively directed towards several MSI logic families containing flip-flops, since Binder et al postulated the explanation for anomalous bit flips in 1975. The test was performed as a result of a joint effort between the Jet Propulsion Laboratory and MIT Lincoln ...
J. P. Woods, D. K. Nichols, W. E. Price
openaire   +1 more source

Accurate Analysis of Single Event Upsets in a Pipelined Microprocessor

Journal of Electronic Testing, 2003
Modern processors embed features such as pipelined execution units and cache memories that can not be directly controlled by programmers through the processor instruction set. As a result, software-based fault injection approaches are even less suitable for assessing the effects of SEUs in modern processors, since they are not able to evaluate the ...
REBAUDENGO, Maurizio   +2 more
openaire   +2 more sources

Single Event Upset Hardening of Interconnects

2016
With advances in technology scaling, circuits are increasingly more sensitive to transients caused by Single Event particles. Hardening techniques for CMOS combinational logic have been developed to address the problems associated with Single Event Transients , but in these designs, SET coupling effects have been ignored.
openaire   +1 more source

Single Event Upset Detection and Correction

10th International Conference on Information Technology (ICIT 2007), 2007
Jawar Singh   +3 more
openaire   +1 more source

Pruning single event upset faults with petri nets

2009 10th Latin American Test Workshop, 2009
Dependability of embedded systems is becoming a serious concern even for mass-market systems. Usually, designs are verified by means of fault injection campaigns, but the length of a thorough test often collides with the severe requirements about design cycle times.
openaire   +1 more source

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