Results 271 to 280 of about 17,927 (312)

EQ-ViT: Algorithm-Hardware Co-Design for End-to-End Acceleration of Real-Time Vision Transformer Inference on Versal ACAP Architecture. [PDF]

IEEE Trans Comput Aided Des Integr Circuits Syst
Dong P, Zhuang J, Yang Z, Ji S, Li Y, Xu D, Huang H, Hu J, Jones AK, Shi Y, Wang Y, Zhou P.   +11 more
europepmc   +1 more source

A 5000 Fps, 4 Megapixel, Radiation-Tolerant, Wafer-Scale CMOS Image Sensor for the Direct Detection of Electrons and Photons. [PDF]

Sensors (Basel)
Scott A, Bauzà C, Bofill-Petit A, Font A, Gargallo M, Gifreu R, Latif K, Mollà Garcia A, Sannino M, Turchetta R.   +9 more
europepmc   +1 more source

TreeHelper: A Wood Transport Authorization and Monitoring System. [PDF]

Sensors (Basel)
Zvîncă AM, Petruc SI, Bogdan R, Marcu M, Popa M.   +4 more
europepmc   +1 more source

Software pipelining of non-vectorizable loosely nested loops

, 1991
Kichang Kim, Alexandru Nicolau
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Voltage regulation in PV-rich distribution networks: an edge pipelined intelligent computing approach. [PDF]

Commun Eng
Li C, Liu J, Liu Q, Li Y, Cao Y, Li Y.
europepmc   +1 more source

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Software pipelining

ACM Computing Surveys, 1995
Utilizing parallelism at the instruction level is an important way to improve performance. Because the time spent in loop execution dominates total execution time, a large body of optimizations focuses on decreasing the time to execute each iteration. Software pipelining is a technique that reforms the loop so that a faster execution rate is realized ...
Vicki H. Allan, Reese B. Jones, Randall M. Lee, Stephen J. Allan   +3 more
openaire   +1 more source

De-pipeline a software-pipelined loop

2003 IEEE International Conference on Acoustics, Speech, and Signal Processing, 2003. Proceedings. (ICASSP '03)., 2003
Software pipelining is a loop optimization technique that has been widely implemented in modem optimizing compilers. In order to utilize fully the instruction level parallelism of the recent VLIW DSP processors, DSP programs have to be optimized by software pipelining.
null Bogong Su, null Jian Wang, null Erh-Wen Hu, J. Manzano   +3 more
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Trace software pipelining

Journal of Computer Science and Technology, 1995
Global software pipelining is a complex but efficient compilation technique to exploit instruction-level parallelism for loops with branches. This paper presents a novel global software pipelining technique, called Trace Software Pipelining, targeted to the instruction-level parallel processors such as Very Long Instruction Word (VLIW) and superscalar ...
Jian Wang, Andreas Krall, M. Anton Ertl
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Software pipelining showdown

Proceedings of the ACM SIGPLAN 1996 conference on Programming language design and implementation, 1996
This paper is a scientific comparison of two code generation techniques with identical goals --- generation of the best possible software pipelined code for computers with instruction level parallelism. Both are variants of modulo scheduling , a framework for generation of software pipelines pioneered by Rau and ...
John Ruttenberg, G. R. Gao, A. Stoutchinin, W. Lichtenstein   +3 more
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Resource-constrained software pipelining

IEEE Transactions on Parallel and Distributed Systems, 1995
This paper presents a software pipelining algorithm for the automatic extraction of fine-grain parallelism in general loops. The algorithm accounts for machine resource constraints in a way that smoothly integrates the management of resource constraints with software pipelining.
A. Aiken, A. Nicolau, S. Novack
openaire   +1 more source