Results 21 to 30 of about 17,927 (312)

Hypernode reduction modulo scheduling [PDF]

, 1995
Software pipelining is a loop scheduling technique that extracts parallelism from loops by overlapping the execution of several consecutive iterations.
Ayguadé Parra, Eduard, González Colás, Antonio María, Llosa Espuny, José Francisco, Valero Cortés, Mateo   +3 more
core   +1 more source

Empowering parallel computing with field programmable gate arrays [PDF]

, 2020
After more than 30 years, reconfigurable computing has grown from a concept to a mature field of science and technology. The cornerstone of this evolution is the field programmable gate array, a building block enabling the configuration of a custom hardware ...
D'Hollander, Erik
core   +2 more sources

Perl module and PISE wrappers for the integrated analysis of sequence data and SNP features

BMC Research Notes, 2009
Background There is a need for software scripts and modules for format parsing, data manipulation, statistical analysis and annotation especially for tasks related to marker identification from sequence data and sequence diversity analysis.
Nayak Spurthi, Reddy P Srinivasa, Jami Anusha, BhanuPrakash A, Jayashree B, Varshney Rajeev K   +5 more
doaj   +1 more source

FPGA Implementation of Image Registration Using Accelerated CNN

Sensors, 2023
Background: Accurate and fast image registration (IR) is critical during surgical interventions where the ultrasound (US) modality is used for image-guided intervention.
Seda Guzel Aydin, Hasan Şakir Bilge
doaj   +1 more source

Co-scheduling hardware and software pipelines [PDF]

Proceedings. Second International Symposium on High-Performance Computer Architecture, 2002
In this paper we propose co-scheduling, a framework for simultaneous design of hardware pipelines structures and software-pipelined schedules. Two important components of the co-scheduling framework are: (1) An extension to the analysis of hardware pipeline design that meets the needs of periodic (or software pipelined) schedules.
Govindarajan, R, Altman, Erik R, Gao, Guang R   +2 more
openaire   +2 more sources

Efficient hardware implementations of high throughput SHA-3 candidates keccak, luffa and blue midnight wish for single- and multi-message hashing [PDF]

, 2010
In November 2007 NIST announced that it would organize the SHA-3 competition to select a new cryptographic hash function family by 2012. In the selection process, hardware performances of the candidates will play an important role.
Akın, Abdulkadir, Akin, Abdulkadir, Aysu, Aydın, Aysu, Aydin, Savas, Erkay, Savaş, Erkay, Ulusel, Onur Can   +6 more
core   +2 more sources

Mining Discriminative K-Mers in DNA Sequences Using Sketches and Hardware Acceleration

IEEE Access, 2020
Extracting discriminative k-mers is an important and challenging problem in DNA sequence analysis with applications in metagenomics and motif discovery.
Antonio Saavedra, Hans Lehnert, Cecilia Hernandez, Gonzalo Carvajal, Miguel Figueroa   +4 more
doaj   +1 more source

SOFTware Pipeline

National Institute for Research in Computer and Control Sciences, Scalbert, Samuel   +1 more
openalex   +2 more sources

Dataflow in MATLAB: Algorithm Acceleration Through Concurrency

IEEE Access, 2017
In this paper, we present a novel Data-Flow architecture for MATLAB. This architecture provides thread-level pipelining of MATLAB functions as well as general concurrency support.
Travis F. Collins, Alexander M. Wyglinski   +1 more
doaj   +1 more source

An OpenCL-based parallel acceleration of aSobel edge detection algorithm Using IntelFPGA technology

South African Computer Journal, 2020
This paper examines the feasibility of using commercial out-of-the-box Reconfigurable Field Programmable Gate Array (FPGA) technology and the OpenCL framework to create efficient Sobel edge-detection implementation, which is considered a fundamental part
Abedalmuhdi Almomany, Ahmad Al-Omari, Amin Jarrah, Mohammed Tawalbeh, Amin Alqudah   +4 more
doaj   +1 more source