A-007 Stack-queue mixed layouts of graph subdivisions
Multi-Modal Optimization of Stacked Chip Macro-Module Layout Based on Memristor-Inspired Evolutionary Game
Radiation Hardness on Dielectric/Ferroelectric Stacked Negative Capacitance Multi-Gate Metal Oxide Semiconductor FETs at Sub-3nm Technology Node: Device to CMOS Inverter Layout
Analysis of mass and thermal transport characteristics in a novel honeycomb stack layout of high-performance proton exchange membrane fuel cells
Thermal Source Layout Optimization of 3d Stacked Ics Using Combination of Deep Neural Network and Pso-Ga Algorithm
, 2014