Results 191 to 200 of about 2,804 (226)

Coverage measurement for software application testing using partially ordered domains and symbolic trajectory evaluation techniques

Third IEEE International Workshop on Electronic Design, Test and Applications (DELTA'06), 2006
Ensuring the functional correctness of a SoC is essential for successful design projects. A proven and effective method from Freescale Semiconductor Australia is to employ software application testing at the pre-silicon simulation stage. This method was formalized and implemented into a Software Application Level Verification Methodology (SALVEM ...
A. Cheng, A. Parashkevov, null Cheng-Chew Lim   +2 more
openaire   +2 more sources

Combining Theorem Proving and Symbolic Trajectory Evaluation in THM&STE

, 2012
In this paper, we present a tool THM&STE, which combines theorem proving with symbolic trajectory evaluation. With the help of theorem proving, a large property is decomposed into smaller properties, which can be handled directly by running STE. Besides the support of decomposition by the classical STE laws, some novel techniques such as simplification
Yongjian Li, Naiju Zeng, William N. N. Hung, Xiaoyu Song   +3 more
openaire   +2 more sources

Exploiting symmetry when verifying transistor-level circuits by symbolic trajectory evaluation: a summary

IEEE Circuits and Systems Magazine, 2001
Summary form only given. We describe the use of symmetry for verification of transistor-level circuits by symbolic trajectory evaluation (STE). We present a new formulation of STE which allows a succinct description of symmetry properties in circuits. Symmetries in circuits are classified as structural symmetries, arising from similarities in circuit ...
M. Pandey, R.E. Bryant
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Explaining Symbolic Trajectory Evaluation by Giving It a Faithful Semantics

, 2006
Symbolic Trajectory Evaluation (STE) is a formal verification technique for hardware. The current STE semantics is not faithful to the proving power of existing STE tools, which obscures the STE theory unnecessarily. In this paper, we present a new closure semantics for STE which does match the proving power of STE model-checkers, and makes STE easier ...
Jan-Willem Roorda, Koen Claessen
openaire   +2 more sources

Automatic Abstraction Refinement for Generalized Symbolic Trajectory Evaluation

Formal Methods in Computer Aided Design (FMCAD'07), 2007
Yan Chen, Yujing He, Fei Xie, Jin Yang
  +4 more sources

Automatic generation of assertions for formal verification of PowerPC microprocessor arrays using symbolic trajectory evaluation

Proceedings of the 35th annual conference on Design automation conference - DAC '98, 1998
For verifying complex sequen tialbloc ks such as microprocessor embedded arrays, the formal method of symbolic trajectory ev aluation (STE) has achieved great success in the past [[3], [5], [6]]. P ast STE methodology for arrays requires manual creation of “assertions” to which both the RTL view and the actual design should be equivalent. In this paper,
Li-C. Wang, Magdy S. Abadir, Nari Krishnamurthy   +2 more
openaire   +2 more sources

Symbolic trajectory evaluation

, 1997
Scott Hazelhurst, Carl-Johan H. Seger
openaire   +2 more sources

Symbolic Trajectory Evaluation

, 2000
Damir A. Jamsek
openaire   +2 more sources

Automatic generation of assertions for formal verification of PowerPC/sup TM /microprocessor arrays using symbolic trajectory evaluation

Proceedings 1998 Design and Automation Conference. 35th DAC. (Cat. No.98CH36175), 2002
L.-C. Wang, M.S. Abadir, N. Krishnamurthy   +2 more
openaire   +2 more sources

Combining Symmetry Reduction with Generalized Symbolic Trajectory Evaluation

The Computer Journal, 2013
Y. Li, N. Zeng, W. N. N. Hung, X. Song
openaire   +2 more sources