Results 251 to 260 of about 4,082,982 (293)
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System-level design guidance using algorithm properties
Proceedings of 1994 IEEE Workshop on VLSI Signal Processing, 2002This paper introduces an approach which provides quantitative information used to aid in making system-level design decisions such as algorithmic or architectural selection. The method is based on the idea of identifying and using the size and structural properties of algorithms, which affect design performance.
L. Guerra, M. Potkonjak, J. Rabaey
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A System-Level Approach to Thermoelectric Material Property Optimization
Journal of Electronic Materials, 2015The opportunities for creating the most effective thermoelectric (TE) material can be maximized by considering the full system for a given application when developing the material. If conversion efficiency is the only consideration in the design of a TE material, then maximizing average ZT over the largest temperature range may be the best choice.
D.T. Crane +5 more
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Deriving Systems Level Security Properties of Component Based Composite Systems
2005 Australian Software Engineering Conference, 2005This paper proposes an approach of defining systems-level security properties of component-based composite systems. It argues that the security properties of a composite system can be viewed either from the end-users’ point of view, or from the software integrators’ point of view.
Khaled M. Khan, Jun Han 0004
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Back-annotation of gate-level power properties into system level descriptions
2014 IEEE 12th International New Circuits and Systems Conference (NEWCAS), 2014It is important to accurately estimate power consumption in early stages of the design in order to avoid costly redesign. System level design consists of defining transaction level (TL) communications between various components that can be either processors or cores described at system level using high level languages such as SystemC.
Najmeh Farajipour Ghohroud +1 more
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Properties First—Correct-By-Construction RTL Design in System-Level Design Flows
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2020This paper presents a new Property-Driven Design (PDD) method that starts from an abstract system model and integrates formal property checking early into a top-down design methodology for register transfer level (RTL) hardware. In PDD the role of formal verification is not limited to “bug hunting” alone.
Tobias Ludwig 0002 +3 more
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System-level Properties as Numerical Invariants
2019This chapter summarizes an attempt to express classical notions of control theory such as stability or robustness using the previously presented invariant-based tools. All numerical tools presented in previous chapters were focused on the precise over-approximation of reachable states.
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Back-annotation of Interconnect Physical Properties for System-Level Crosstalk Modeling
2019 IEEE European Test Symposium (ETS), 2019As digital design moves into higher abstraction levels, chip-level communications become more complex, thus harder to consider low-level interconnection signal effects. Abstract interconnect models are required in order to be able to bring signal integrity issues such as crosstalk into the hands of the high-level system designer.
Rezgar Sadeghi +3 more
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Validation of System-level Properties at Code Level
2019This chapter claims that code generation can be adapted to enable the expression of system-level properties at code level, and be later proved with respect to the code semantics. All previous analyses were performed on discrete dynamical systems models.
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The PMC system level fault model: cardinality properties of the implied faulty sets
IEEE Transactions on Computers, 1989One aspect of the PMC system level fault model, the properties of the implied faulty sets, is considered. For tau -diagnosable systems that have at most tau faulty units, lower bounds on the cardinality of the maximal implied faulty sets are given. Then it is shown that these bounds are greatest lower bounds, and it is indicated how these results can ...
Mary Ann Kennedy, Gerard G. L. Meyer
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From RTL IP to functional system-level models with extra-functional properties
Proceedings of the eighth IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis, 2012The paper presents a novel abstraction methodology for generating time- and power-annotated TLM models from synthesizable RTL descriptions. The proposed techniques allow the integration of existing RTL IP components into virtual platforms for early software development and platform design, configuration, and exploration.
D. Lorenz +4 more
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