Results 231 to 240 of about 93,314 (285)

Translating systolic arrays into instruction systolic arrays

Proceedings of the 1988 ACM sixteenth annual conference on Computer science - CSC '88, 1988
An instruction systolic array is a programmable systolic array. Instructions and mask bits are pumped through the array as well as data. It offers cost-benefit advantages over systolic arrays because one array can be used for multiple applications.
Adrian Vrouwenvelder, Keith R. Allen, Roy P. Pargas   +2 more
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The Systolic Reconfigurable Mesh

Parallel Processing Letters, 2004
In this paper, we introduce the Systolic Reconfigurable Mesh (SRM), which combines aspects of the reconfigurable mesh with that of systolic arrays. Every processor controls a local switch that can be reconfigured during every clock cycle in order to control the physical connections between its four bi-directional bus lines. Data is input on one side of
Mary Mehrnoosh Eshaghian, Russ Miller
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Systolic model and systolic geometry

1988., IEEE International Symposium on Circuits and Systems, 2003
The lack of a precise model for systolic algorithms has been hindering progress in the automatic synthesis of systolic arrays. The author proposes a model that encompasses a very large class of algorithms but is still restrictive enough so that mappings of such algorithms onto systolic architectures whose time performance is within a known factor of ...
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Systolic & semi-systolic digit serial multipliers

1987 IEEE 8th Symposium on Computer Arithmetic (ARITH), 1987
Digit serial data transmission can be used to an advantage in the design of special purpose processors where communication issues dominate and where digit pipelining can be used to maintain high data rates. VLSI signal processing is one such problem domain. We propose designs of systolic and semi-systolic digit serial multipliers. These multipliers are
Poras T. Balsara, Robert Michael Owens
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Mirroring: a technique for pipelining semi-systolic and systolic arrays

Integration, 1997
Summary: We present a transformation, called mirroring, that enables pipelining in semi-systolic and systolic linear arrays. Mirroring doubles the throughput of semi-systolic arrays and increases the throughput of systolic arrays by one third.
Michael Braun 0002, Guy Even, Thomas Walle   +2 more
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Systolic Click and Late Systolic Murmur in a Young Woman

Chest, 1974
An asymptomatic young woman with a systolic click and late systolic murmur is discussed. Phonocardiograms, multiple cardiograms, carotid tracing, and echocardiogram revealed a prolapse of the posterior mitral leaflet. Angiocardiogram confirmed the diagnosis made by use of the noninvasive methods.
A A, Luisada, P, Bhat
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Systolic genetic search, a systolic computing-based metaheuristic

Soft Computing, 2014
In this paper, we propose a new parallel optimization algorithm that combines ideas from the fields of metaheuristics and Systolic Computing. The algorithm, called Systolic Genetic Search (SGS), is designed to explicitly exploit the high degree of parallelism available in modern Graphics Processing Unit (GPU) architectures.
Martín Pedemonte, Francisco Luna 0001, Enrique Alba 0001   +2 more
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Derivation of Systolic Programs

1994 International Conference on Parallel Processing Vol. 3, 1994
We describe a methodology for mapping linear recurrence equations to a spectrum of systolic architectures. First, we design a systolic program in a very general architecture referred to as Basic Systolic Architecture and establish the correctness of the implementation.
Ladan Kazerouni, Basant Rajan, R. K. Shyamasundar   +2 more
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Estimation of Systolic Pulmonary Pressure and Right Ventricular Systolic Impairment

Journal of Cardiac Failure, 2012
In our opinion, asserting with confidence that RV systolic impairment worsens echocardiographic estimation of PASP is not possible. We therefore regard a study specifically designed to address this question to be needed.
Magnino C, Milan A, VEGLIO, Franco
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Systolic Algorithms and Systolic Processors

1992
The systolic processing provides a possibility to solve a large number of standard problems on multicellular computing devices with autonomous cells. Interruptions by the host computer are necessary only for changing of the computing mode and occurs only a few times while solving the problem. They arise on the starting and final phases and sometimes on
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