Results 81 to 90 of about 2,053,524 (303)

Complete and efficient methods for supporting side effects in independent/restricted and-parallelism [PDF]

, 1989
It has been shown that it is possible to exploit Independent/Restricted And-parallelism in logic programs while retaining the conventional "don't know" semantics of such programs.
Muthukumar, Kalyan, Hermenegildo, Manuel V., K. Muthukumar, M. Hermenegildo   +3 more
core  

Experimental Demonstration of Temporally Aware Fault‐Tolerant Sensor Fusion Using Memristive Associative Learning

Advanced Electronic Materials, EarlyView.
In dynamic driving scenarios, the proposed approach ensures only temporally aligned sensor inputs to make driving decisions, preventing false activations. By enabling selective hardware‐level learning, it achieves fast, reliable responses under noisy conditions.
Kapil Bhardwaj, Ashfak Nehal, Dmitrii Semenov, Roman Sotner, Sayani Majumdar   +4 more
wiley   +1 more source

Incremental Task Graph Partitioning with Constrained Parallelism

Task graph programming models (TGPMs) are widely used in parallelizing irregular applications because they allow developers to express and optimize task parallelism in a top-down manner.
Che Chang, Boyang Zhang, Chih-Chun Chang, Tsung-Wei Huang, Yi-Hua Chung   +4 more
core   +1 more source

Stochastic‐MTJ Sampler Arrays for In‐Array Monte–Carlo Estimation

Advanced Electronic Materials, EarlyView.
A low‐energy‐barrier magnetic tunnel junction array is operated as a probability‐domain sampler: each cell's random switching, programmed through a shared digital‐to‐analog converter, makes the per‐column multiply–accumulate an unbiased Monte–Carlo expectation estimator that returns both a mean and a calibrated uncertainty.
Ran Zhang, Nellie Laleni, Sina Ranjbar, Andreas Tsiougkos, Nandakishor Yadav, Vasilis Pavlidis, Thomas Kämpfe   +6 more
wiley   +1 more source

Design of FPGA-Based Accelerator for Convolutional Neural Network under Heterogeneous Computing Framework with OpenCL

International Journal of Reconfigurable Computing, 2018
CPU has insufficient resources to satisfy the efficient computation of the convolution neural network (CNN), especially for embedded applications. Therefore, heterogeneous computing platforms are widely used to accelerate CNN tasks, such as GPU, FPGA ...
Li Luo, Yakun Wu, Fei Qiao, Yi Yang, Qi Wei, Xiaobo Zhou, Yongkai Fan, Shuzheng Xu, Xinjun Liu, Huazhong Yang   +9 more
doaj   +1 more source

Predictable and Scalable Analog Matrix–Vector Multiplication in Memristor Crossbars via Closed‐Form Wire‐Resistance Compensation

Advanced Electronic Materials, EarlyView.
Wire resistance and sneak paths severely compromise the performance of large memristor crossbars. A predictive closed‐form distributed line‐resistance model, combined with a fourmatrix geometry‐averaging algorithm, eliminates these parasitic limitations.
Davide Rossetti, Yichun Xu, Ludovica Asselta, J. Joshua Yang, R. Stanley Williams, Fernando Corinto   +5 more
wiley   +1 more source

Autonomous AI‐Driven Design for Skin Product Formulations

Advanced Intelligent Discovery, EarlyView.
This review presents a comprehensive closed‐loop framework for autonomous skin product formulation design. By integrating artificial intelligence‐driven experiment selection with automated multi‐tiered assays, the approach shifts development from trial‐and‐error to intelligent optimisation.
Yu Zhang, Yongrui Xiao, Chunlin Chen, Dimitrios Tsaoulidis, Kai Yang, Tao Chen   +5 more
wiley   +1 more source

Enabling task level parallelism in HandelC [PDF]

, 2007
Thesis (M.S.)--University of Kansas, Electrical Engineering & Computer Science, 2007.HandelC is a programming language used to target hardware and is similar in syntax to ANSI-C.
AbuYasin, Thamer S.
core   +3 more sources

Distributed Memory Implementation of Bron-Kerbosch Algorithm

IEEE Access
This paper proposes a parallel implementation of the Bron-Kerbosch algorithm, which finds all maximal cliques in large, complex graphs using CPU and thread-level parallelism and distributed memory with multiple cores. With the growing size and complexity
Tejas Ravindra Rote, Murugan Krishnammorthy, Ansh Bhatia, Rishu Yadav, S. P. Raja   +4 more
doaj   +1 more source

Parametric Analysis of Spiking Neurons in 16 nm Fin Field‐Effect Transistor Technology

Advanced Intelligent Discovery, EarlyView.
Energy efficient computing has driven a shift toward brain‐inspired neuromorphic hardware. This study explores the design of three distinct silicon neuron topologies implemented in 16 nm fin field‐Effect transistor technology. While the Axon‐Hillock design achieves gigahertz throughput, its functional fragility persists. The Morris–Lecar model captures
Logan Larsh, Raiyan Siddique, Sarah S. Sharif, Yaser Mike Banad   +3 more
wiley   +1 more source