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Design for testability reuse in synthesis for testability
Proceedings. XII Symposium on Integrated Circuits and Systems Design (Cat. No.PR00387), 2003This paper presents our Design for Testability reuse approach implemented in the allocation for testability system IDAT. In the context of High-Level Synthesis for Testability, the allocation for testability process mainly consists in searching for the best cost/quality trade-off between the designer requirements and testability means which can be ...
Bukovjan, Peter +2 more
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A survey on software testability [PDF]
Information and Software Technology, 2019 Context: Software testability is the degree to which a software system or a unit under test supports its own testing. To predict and improve software testability, a large number of techniques and metrics have been proposed by both practitioners and researchers in the last several decades. Reviewing and getting an overview of the entire state-of-the-art
Vahid Garousi +2 more
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ACM Transactions on Computation Theory, 2014
This article studies property testing for NP optimization problems with parameter k under the general graph model with an augmentation of random edge sampling capability. It is shown that a variety of such problems, including k -Vertex Cover, k -Feedback Vertex Set,
Kazuo Iwama, Yuichi Yoshida
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This article studies property testing for NP optimization problems with parameter k under the general graph model with an augmentation of random edge sampling capability. It is shown that a variety of such problems, including k -Vertex Cover, k -Feedback Vertex Set,
Kazuo Iwama, Yuichi Yoshida
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Microprocessors and Microsystems, 1992
A new approach to testing based on boundary scan is discussed. This technique gives access to individual chip pins by including a little standardized circuitry and a test access port (TAP) on every IC. Boundary scan basics are reviewed, and three principal types of tests that can be performed with the boundary-scan register are described.
Colin M. Maunder, Rodham E. Tulloss
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A new approach to testing based on boundary scan is discussed. This technique gives access to individual chip pins by including a little standardized circuitry and a test access port (TAP) on every IC. Boundary scan basics are reviewed, and three principal types of tests that can be performed with the boundary-scan register are described.
Colin M. Maunder, Rodham E. Tulloss
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Proceedings of the 4th ACM international workshop on Storage security and survivability, 2008
A key challenge in litigation is verifying that all relevant case content has been produced. Adding to the challenge is the fact that litigating parties are both bound to produce relevant documents and bound to protect private information (e.g. medical information).
Philippe Golle +2 more
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A key challenge in litigation is verifying that all relevant case content has been produced. Adding to the challenge is the fact that litigating parties are both bound to produce relevant documents and bound to protect private information (e.g. medical information).
Philippe Golle +2 more
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M-testability: an approach for data-path testability evaluation
Proceedings of European Design and Test Conference EDAC-ETC-EUROASIC, 2002In this paper, a new M-testability approach is introduced. M-testability is based on a new Variable Testability Measure (VTM) appropriate in high-level synthesis. It is shown that VTM is a generalization of the C-testability concept which is extended to M-testability to deal with more general arrays such as those of non identical cells or functional ...
Mohamed Jamoussi, Bozena Kaminska
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SIAM Journal on Computing, 1991
To capture the informal notion of ``having an efficient partial membership test'', the authors introduce near-testable (\(NT\)) sets. For any such set \(S\) one can determine in polynomial time whether exactly one of a string and its predecessor belongs to \(S\).
Judy Goldsmith +3 more
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To capture the informal notion of ``having an efficient partial membership test'', the authors introduce near-testable (\(NT\)) sets. For any such set \(S\) one can determine in polynomial time whether exactly one of a string and its predecessor belongs to \(S\).
Judy Goldsmith +3 more
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IEEE Transactions on Computers, 1984
A major problem in self testing with random inputs is verification of the test quality, i.e., the computation of the fault coverage. The brute-force approach of using full-fault simulation does not seem attractive because of the logic structure volume, and the CPU time encountered. A new approach is therefore necessary.
Jacob Savir +2 more
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A major problem in self testing with random inputs is verification of the test quality, i.e., the computation of the fault coverage. The brute-force approach of using full-fault simulation does not seem attractive because of the logic structure volume, and the CPU time encountered. A new approach is therefore necessary.
Jacob Savir +2 more
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Microprocessors and Microsystems, 1979
Abstract In the laboratory, a designer may conveniently analyse microprocessor circuits and their peripherals by means of suitable logic analysers. This is possible because he will have a detailed knowledge of his system and the time to learn the optimum methods of using his analyser. Once this system is a part of a product, it would be preferable if
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Abstract In the laboratory, a designer may conveniently analyse microprocessor circuits and their peripherals by means of suitable logic analysers. This is possible because he will have a detailed knowledge of his system and the time to learn the optimum methods of using his analyser. Once this system is a part of a product, it would be preferable if
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Design for testability—A survey
Proceedings of the IEEE, 1982This paper discusses the basics of design for testability. A short review of testing is given along with some reasons why one should test. The different techniques of design for testability are discussed in detail. These include techniques which can be applied to today's technologies and techniques which have been recently introduced and will soon ...
Thomas W. Williams, Kenneth P. Parker
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