Cycle-accurate evaluation of reconfigurable photonic networks-on-chip [PDF]
, 2010 There is little doubt that the most important limiting factors of the performance of next-generation Chip Multiprocessors (CMPs) will be the power efficiency and the available communication speed between cores.
Artundo, Iñigo +4 more
core +1 more source
On the suitability and development of layout templates for analog layout reuse and layout-aware synthesis [PDF]
, 2005 Accelerating the synthesis of increasingly complex analog integrated circuits is key to bridge the widening gap between what we can integrate and what we can design while meeting ever-tightening time-to-market constraints.
Castro López, Rafael +2 more
core +1 more source
Synchronization of Nonlinear Circuits in Dynamic Electrical Networks with General Topologies [PDF]
, 2013 Sufficient conditions are derived for global asymptotic synchronization in a system of identical nonlinear electrical circuits coupled through linear time-invariant (LTI) electrical networks.
Dhople, Sairaj +3 more
core +1 more source
An Integrated Subharmonic Coupled-Oscillator Scheme for a 60-GHz Phased-Array Transmitter [PDF]
, 2006 This paper describes the design of an integrated coupled-oscillator array in SiGe for millimeter-wave applications. The design focuses on a scalable radio architecture where multiple dies are tiled to form larger arrays. A 2 × 2 oscillator array for a 60-
Babakhani, Aydin +3 more
core +1 more source
Automatic synthesis of analog layout : a survey [PDF]
, 1990 A review of recent research in the automatic synthesis of physical geometry for analog integrated circuits is presented. On introduction, an explanation of the difficulties involved in analog layout as opposed to digital layout is covered.
Rentmeesters, Mark J.
core
Characterisation and macro-modeling of patterned micronic and nano-scale dummy metal-fills in integrated circuits [PDF]
, 2009 In this paper, a wideband characterization and macro-modeling of patterned micronic and nano-scale dummy metal-fills is presented. Impacts of patterned dummy metal-fill topologies including square, cross, vertical and horizontal shaped arrays on ...
Bajon, Damienne, Wane, Sidina
core +1 more source
Ultra Low-Power Analog Median Filters [PDF]
, 2013 The design and implementation of three analog median filter topologies, whose transistors operate in the deep weak-inversion region, is described. The first topology is a differential pairs array, in which drain currents are driven into two nodes in a ...
Diaz-Sanchez, A. +5 more
core +1 more source
Simulation-based high-level synthesis of Nyquist-rate data converters using MATLAB/SIMULINK [PDF]
, 2005 This paper presents a toolbox for the simulation, optimization and high-level synthesis of Nyquist-rate Analog-to-Digital (A/D) and Digital-to-Analog (D/A) Converters in MATLAB®.
Delgado Restituto, Manuel +3 more
core +1 more source
Column-row addressing of thermo-optic phase shifters for controlling large silicon photonic circuits [PDF]
, 2020 We demonstrate a time-multiplexed row-column addressing scheme to drive thermo-optic phase shifters in a silicon photonic circuit. By integrating a diode in series with the heater, we can connect $N \times M$ heaters in an matrix topology to $N$ row and $
Alves Júnior, Antônio Ribeiro +5 more
core +1 more source
Fully integrated CMOS power amplifier design using the distributed active-transformer architecture [PDF]
, 2002 A novel on-chip impedance matching and power-combining method, the distributed active transformer is presented. It combines several low-voltage push-pull amplifiers efficiently with their outputs in series to produce a larger output power while ...
Aoki, Ichiro +3 more
core +1 more source